/pdf/self-assembled-monolayers-of-thiolates-on-metals-as-a-form-1neb0hj3k4.pdf

Self-assembled monolayers of thiolates on metals as a form of nanotechnology.

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Silicon nanowires can be prepared with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source-drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V‚s with peak values of 2000 nS and 1350 cm 2 /V‚s, respectively. The comparison of these results and other key parameters with state-of-the-art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.

http://cml.harvard.edu/assets/nanoLett3_149.pdf

High Performance Silicon Nanowire Field Effect Transistors

Manipulating matter at the nanometre scale is important for many electronic, chemical and biological advances, but present solid-state fabrication methods do not reproducibly achieve dimensional control at the nanometre scale. Here we report a means of fashioning matter at these dimensions that uses low-energy ion beams and reveals surprising atomic transport phenomena that occur in a variety of materials and geometries. The method is implemented in a feedback-controlled sputtering system that provides fine control over ion beam exposure and sample temperature. We call the method "ion-beam sculpting", and apply it to the problem of fabricating a molecular-scale hole, or nanopore, in a thin insulating solid-state membrane. Such pores can serve to localize molecular-scale electrical junctions and switches and function as masks to create other small-scale structures. Nanopores also function as membrane channels in all living systems, where they serve as extremely sensitive electro-mechanical devices that regulate electric potential, ionic flow, and molecular transport across cellular membranes. We show that ion-beam sculpting can be used to fashion an analogous solid-state device: a robust electronic detector consisting of a single nanopore in a Si3N4 membrane, capable of registering single DNA molecules in aqueous solution.

/pdf/ion-beam-sculpting-at-nanometre-length-scales-40212kzmit.pdf

Ion-beam sculpting at nanometre length scales

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Stanley Wolf

Papers

Silicon Processing for the VLSI Era