Localized surface plasmon resonance (LSPR) in semiconductor nanocrystals (NCs) that results in resonant absorption, scattering, and near field enhancement around the NC can be tuned across a wide optical spectral range from visible to far-infrared by synthetically varying doping level, and post synthetically via chemical oxidation and reduction, photochemical control, and electrochemical control In this review, we will discuss the fundamental electromagnetic dynamics governing light matter interaction in plasmonic semiconductor NCs and the realization of various distinctive physical properties made possible by the advancement of colloidal synthesis routes to such NCs Here, we will illustrate how free carrier dielectric properties are induced in various semiconductor materials including metal oxides, metal chalcogenides, metal nitrides, silicon, and other materials We will highlight the applicability and limitations of the Drude model as applied to semiconductors considering the complex band structures 

Localized Surface Plasmon Resonance in Semiconductor Nanocrystals

Incorporating semiconductors as active media into metamaterials offers opportunities for a wide range of dynamically switchable/tunable, technologically relevant optical functionalities enabled by strong, resonant light-matter interactions within the semiconductor. Here, a germanium-thin-film-based flexible metaphotonic device for ultrafast optical switching of terahertz radiation is experimentally demonstrated. A resonant transmission modulation depth of 90% is achieved, with an ultrafast full recovery time of 17 ps. An observed sub-picosecond decay constant of 670 fs is attributed to the presence of trap-assisted recombination sites in the thermally evaporated germanium film.

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Ultrafast All-Optical Switching of Germanium-Based Flexible Metaphotonic Devices.

Abstract The coupling between light and collective oscillations of free carriers at metallic surfaces and nanostructures is at the origin of one of the main fields of nanophotonics: plasmonics. The potential applications offered by plasmonics range from biosensing to solar cell technologies and from nonlinear optics at the nanoscale to light harvesting and extraction in nanophotonic devices. Heavily doped semiconductors are particularly appealing for the infrared spectral window due to their compatibility with microelectronic technologies, which paves the way toward their integration in low-cost, mass-fabricated devices. In addition, their plasma frequency can be tuned chemically, optically, or electrically over a broad spectral range. This review covers the optical properties of the heavily doped conventional semiconductors such as Ge, Si, or III–V alloys and how they can be successfully employed in plasmonics. The modeling of their specific optical properties and the technological processes to realize nanoantennas, slits, or metasurfaces are presented. We also provide an overview of the applications of this young field of research, mainly focusing on biosensing and active devices, among the most recent developments in semiconductor plasmonics. Finally, an outlook of further research directions and the potential technological transfer is presented.

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Semiconductor infrared plasmonics

https://iopscience.iop.org/article/10.1088/0268-1242/31/10/103001/pdf

A review of thermal processing in the subsecond range: semiconductors and beyond

Chalcogen-hyperdoped silicon shows potential applications in silicon-based infrared photodetectors and intermediate band solar cells. Due to the low solid solubility limits of chalcogen elements in silicon, these materials were previously realized by femtosecond or nanosecond laser annealing of implanted silicon or bare silicon in certain background gases. The high energy density deposited on the silicon surface leads to a liquid phase and the fast recrystallization velocity allows trapping of chalcogen into the silicon matrix. However, this method encounters the problem of surface segregation. In this paper, we propose a solid phase processing by flash-lamp annealing in the millisecond range, which is in between the conventional rapid thermal annealing and pulsed laser annealing. Flash lamp annealed selenium-implanted silicon shows a substitutional fraction of ~ 70% with an implanted concentration up to 2.3%. The resistivity is lower and the carrier mobility is higher than those of nanosecond pulsed laser annealed samples. Our results show that flash-lamp annealing is superior to laser annealing in preventing surface segregation and in allowing scalability.

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Hyperdoping silicon with selenium: solid vs. liquid phase epitaxy

A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.

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Ultra-doped n-type germanium thin films for sensing in the mid-infrared

We present the development, optimization and fabrication of high carrier mobility materials based on GeOI wafers co-doped with Sn and P. The Ge thin films were fabricated using plasma-enhanced chemical vapour deposition followed by ion implantation and explosive solid phase epitaxy, which is induced by millisecond flash lamp annealing. The influence of the recrystallization mechanism and co-doping of Sn on the carrier distribution and carrier mobility both in n-type and p-type GeOI wafers is discussed in detail. This finding significantly contributes to the state-of-the-art of high carrier mobility-GeOI wafers since the results are comparable with GeOI commercial wafers fabricated by epitaxial layer transfer or SmartCut technology.

http://iopscience.iop.org/article/10.1088/0268-1242/31/10/105012/pdf

Enhancement of carrier mobility in thin Ge layer by Sn co-doping

Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies ( f T, f max), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/μm. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/μm. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.

Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design

We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.

Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs

Vertical III-V heterostructure MOSFETs exhibit outstanding performance at reduced supply voltages. In this letter, we report on a novel process of extending high-speed device operation towards higher voltages. The device vertical geometry allows for engineering a field plate by covering the nanowire drain area with a 10-nm-thick SiO2 film. The film acts as a field moderator in the device drain region. Reference devices without a field plate exhibit a transconductance of 2.5 mS/ $\mu \text{m}$ , while devices with a 120-nm-long field plate show 1.5 mS/ $\mu \text{m}$ but a three times increase in breakdown voltage. Measurements show that the field-screening effect attributes to reduced band-to-band tunneling and impact ionization, thereby reducing the parasitic bipolar effect in the MOSFET channel as well. The devices show promise in applications in circuits and systems requiring large power-handling.

Stefan Andric

Papers

Ultra-doped n-type germanium thin films for sensing in the mid-infrared

Enhancement of carrier mobility in thin Ge layer by Sn co-doping

Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design

Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs

Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs With a Field Plate