Stephen M. Trimberger

Bio: Stephen M. Trimberger is an academic researcher from Xilinx. The author has contributed to research in topics: Programmable logic device & Programmable logic array. The author has an hindex of 53, co-authored 211 publications receiving 8806 citations.

A time-multiplexed FPGA

Abstract: This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 30 ns. Inactive memory is accessible as block RAM for applications. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware.

Field-Programmable Gate Array Technology

Abstract: Preface. 1: Introduction. 1.1. Logic Implementation Options. 1.2. What is an FPGA? 1.3. Advantages of FPGAs. 1.4. Disadvantages of FPGAs. 1.5. Technology Trends. 1.6. Designing for FPGAs. 1.7. Outline of Subsequent Chapters. 1.8. References. 2: SRAM Programmable FPGAs. 2.1. Introduction. 2.2. Programming Technology. 2.3. Device Architecture. 2.4. Software. 2.5. The Future. 2.6. Design Applications. 2.7. Acknowledgements 2.8. References. 3. Antifuse Programmed FPGAs. 3.1. Introduction. 3.2. Programming Technology. 3.3. Device Architecture. 3.4. Software. 3.5. The Future. 3.6. Design Applications. 3.7. Acknowledgements. 3.8. References. 4. Erasable Programmable Logic Devices. 4.1. Introduction. 4.2. Programming Technology. 4.3. Device Architecture. 4.4. Software. 4.5. The Future. 4.6. Design Applications. 4.7. References. Index.

Method of time multiplexing a programmable logic device

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Time multiplexed programmable logic device

Abstract: A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiments, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof. The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This reconfiguration allows the PLD to function in one of N configurations, wherein N is equal to the maximum number of memory cells assigned to each programmable point. In this manner, a PLD with a number M of actual CLBs functions as if it includes M times N effective CLBs.

Integrated circuit with field programmable and application specific logic areas

Abstract: A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Reconfigurable computing: a survey of systems and software

Abstract: Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.

What is a tutorial

Abstract: There are two kinds of tutorial articles: those that provide a primer on an established topic and those that let us in on the ground floor of something of emerging importance. The first type of tutorial can have a noted expert who has been gracious (and brave) enough to write a field guide about a particular topic. The other sort of tutorial typically involves researchers who have each been laboring on a topic for some years. Both sorts of tutorial articles are very much desired. But we, as an editorial board for both Systems and Transactions, know that there has been no logical place for them in the AESS until this series was started several years ago. With these tutorials, we hope to continue to give them a home, a welcome, and provide a service to our membership. We do not intend to publish tutorials on a regular basis, but we hope to deliver them once or twice per year. We need and welcome good, useful tutorial articles (both kinds) in relevant AESS areas. If you, the reader, can offer a topic of interest and an author to write about it, please contact us. Self-nominations are welcome, and even more ideal is a suggestion of an article that the editor(s) can solicit. All articles will be reviewed in detail. Criteria on which they will be judged include their clarity of presentation, relevance, and likely audience, and, of course, their correctness and scientific merit. As to the mathematical level, the articles in this issue are a good guide: in each case the author has striven to explain complicated topics in simple-well, tutorial-terms. There should be no (or very little) novel material: the home for archival science is the Transactions Magazine, and submissions that need to be properly peer reviewed would be rerouted there. Likewise, articles that are interesting and descriptive, but lack significant tutorial content, ought more properly be submitted to the Systems Magazine.

Multifactorial optimization system and method

Abstract: A method for providing unequal allocation of rights among agents while operating according to fair principles, comprising assigning a hierarchal rank to each agent; providing a synthetic economic value to a first set of agents at the a high level of the hierarchy; allocating portions of the synthetic economic value by the first set of agents to a second set of agents at respectively different hierarchal rank than the first set of agents; and conducting an auction amongst agents using the synthetic economic value as the currency. A method for allocation among agents, comprising assigning a wealth generation function for generating future wealth to each of a plurality of agents, communicating subjective market information between agents, and transferring wealth generated by the secure wealth generation function between agents in consideration of a market transaction. The method may further comprise the step of transferring at least a portion of the wealth generation function between agents.

Fast Regular Expression Matching Using FPGAs

Abstract: This paper presents an efficient method for finding matches to a given regular expression in given text using FPGAs. To match a regular expression of length n, a serial machine requires 0(2^n) memory and takes 0(1) time per text character. The proposed approach reqiures only 0(n^2) space and still process a text character in 0(1) time (one clock cycle).The improvement is due to the Nondetermineistic Finite Automaton (NFA) used to perform the matching. As far as the authors are aware, this is the first prctical use of a nondeterministic state machine on programmable logic. Furthermore, the paper presents a simple, fast algorithm that quickly constructs the NFA for the given regular expression. Fast NFA construction is crucial because the NFA structure depends on the regular expression, which is known only at runtime. Implementations of the algorithm for conventional FPGAs and the self-reconfigurable Gate Array (SRGA) are described. To evaluate performance, the NFA logic was mapped onto the Virtex XCV100 FPGA and the SRGA. Also, the performance of GNU grep for matching regular expressions was evaluated on an 800 MHz Pentium III machine. The proposed approach was faster than best case grep performance in most cases. It was orders of magnitude faster than worst case grep performance. Logic for the largest NFA considered fit in less than a 1000 CLBs while DFA storage for grep in the worst case consumed a few hundred megabytes.

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Abstract: The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. · Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes · Views of FPGA programming beyond Verilog/VHDL · Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways