Stephen Y. Chou

Bio: Stephen Y. Chou is an academic researcher from Princeton University. The author has contributed to research in topics: Nanoimprint lithography & Lithography. The author has an hindex of 81, co-authored 402 publications receiving 28486 citations. Previous affiliations of Stephen Y. Chou include Massachusetts Institute of Technology & Stanford University.

Imprint of sub-25 nm vias and trenches in polymers

Abstract: A nanoimprint process that presses a mold into a thin thermoplastic polymer film on a substrate to create vias and trenches with a minimum size of 25 nm and a depth of 100 nm in the polymer has been demonstrated. Furthermore, the imprint process has been used as a lithography process to fabricate sub‐25 nm diameter metal dot arrays of a 100 nm period in a lift‐off process. It was found that the nanostructures imprinted in the polymers conform completely with the geometry of the mold. At present, the imprinted size is limited by the size of the mold being used; with a suitable mold, the imprint process should mold sub‐10 nm structures with a high aspect ratio in polymers. The nanoimprint process offers a low cost method for mass producing sub‐25 nm structures and has the potential to become a key nanolithography method for future manufacturing of integrated circuits and integrated optics.

Imprint Lithography with 25-Nanometer Resolution

Abstract: A high-throughput lithographic method with 25-nanometer resolution and smooth vertical sidewalls is proposed and demonstrated. The technique uses compression molding to create a thickness contrast pattern in a thin resist film carried on a substrate, followed by anisotropic etching to transfer the pattern through the entire resist thickness. Metal patterns with a feature size of 25 nanometers and a period of 70 nanometers were fabricated with the use of resist templates created by imprint lithography in combination with a lift-off process. With further development, imprint lithography should allow fabrication of sub-10-nanometer structures and may become a commercially viable technique for manufacturing integrated circuits and other nanodevices.

Sub-10 nm imprint lithography and applications

Abstract: New developments, further details, and applications of imprint lithography are presented. Arrays of 10 nm diameter and 40 nm period holes were imprinted not only in polymethylmethacrylate (PMMA) on silicon, but also in PMMA on gold substrates. The smallest hole diameter imprinted in PMMA is 6 nm. All the PMMA patterns were transferred to a metal using a liftoff. In addition, PMMA mesa’s of a size from 45 nm to 50 μm were obtained in a single imprint. Moreover, imprint lithography was used to fabricate the silicon quantum dot, wire, and ring transistors, which showed the same behavior as those fabricated using electron (e)-beam lithography. Finally, imprint lithography was used to fabricate nanocompact disks with 10 nm features and 400 Gbits/in.2 data density—near three orders of magnitude higher than current critical dimensions (CDs). A silicon scanning probe was used to read back the data successfully. The study of wear indicates that due to the ultrasmall force in tapping mode, both the nano-CD and the ...

Deterministic hydrodynamics: Taking blood apart

Abstract: We show the fractionation of whole blood components and isolation of blood plasma with no dilution by using a continuous-flow deterministic array that separates blood components by their hydrodynamic size, independent of their mass. We use the technology we developed of deterministic arrays which separate white blood cells, red blood cells, and platelets from blood plasma at flow velocities of 1,000 μm/sec and volume rates up to 1 μl/min. We verified by flow cytometry that an array using focused injection removed 100% of the lymphocytes and monocytes from the main red blood cell and platelet stream. Using a second design, we demonstrated the separation of blood plasma from the blood cells (white, red, and platelets) with virtually no dilution of the plasma and no cellular contamination of the plasma.

Fabrication of 5 nm linewidth and 14 nm pitch features by nanoimprint lithography

Abstract: We report advances in nanoimprint lithography, its application in nanogap metal contacts, and related fabrication yield. We have demonstrated 5nm linewidth and 14nm linepitch in resist using nanoimprint lithography at room temperature with a pressure less than 15psi. We fabricated gold contacts (for the application of single macromolecule devices) with 5nm separation by nanoimprint in resist and lift-off of metal. Finally, the uniformity and manufacturability of nanoimprint over a 4in. wafer were demonstrated.

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

Spintronics: Fundamentals and applications

Abstract: Spintronics, or spin electronics, involves the study of active control and manipulation of spin degrees of freedom in solid-state systems. This article reviews the current status of this subject, including both recent advances and well-established results. The primary focus is on the basic physical principles underlying the generation of carrier spin polarization, spin dynamics, and spin-polarized transport in semiconductors and metals. Spin transport differs from charge transport in that spin is a nonconserved quantity in solids due to spin-orbit and hyperfine coupling. The authors discuss in detail spin decoherence mechanisms in metals and semiconductors. Various theories of spin injection and spin-polarized transport are applied to hybrid structures relevant to spin-based devices and fundamental studies of materials properties. Experimental work is reviewed with the emphasis on projected applications, in which external electric and magnetic fields and illumination by light will be used to control spin and charge dynamics to create new functionalities not feasible or ineffective with conventional electronics.

Large Area, Few-Layer Graphene Films on Arbitrary Substrates by Chemical Vapor Deposition

Abstract: In this work we present a low cost and scalable technique, via ambient pressure chemical vapor deposition (CVD) on polycrystalline Ni films, to fabricate large area (∼cm2) films of single- to few-layer graphene and to transfer the films to nonspecific substrates. These films consist of regions of 1 to ∼12 graphene layers. Single- or bilayer regions can be up to 20 μm in lateral size. The films are continuous over the entire area and can be patterned lithographically or by prepatterning the underlying Ni film. The transparency, conductivity, and ambipolar transfer characteristics of the films suggest their potential as another materials candidate for electronics and opto-electronic applications.

The path to ubiquitous and low-cost organic electronic appliances on plastic

Abstract: Organic electronics are beginning to make significant inroads into the commercial world, and if the field continues to progress at its current, rapid pace, electronics based on organic thin-film materials will soon become a mainstay of our technological existence. Already products based on active thin-film organic devices are in the market place, most notably the displays of several mobile electronic appliances. Yet the future holds even greater promise for this technology, with an entirely new generation of ultralow-cost, lightweight and even flexible electronic devices in the offing, which will perform functions traditionally accomplished using much more expensive components based on conventional semiconductor materials such as silicon.

Large-area ultrathin films of reduced graphene oxide as a transparent and flexible electronic material

Abstract: The integration of novel materials such as single-walled carbon nanotubes and nanowires into devices has been challenging, but developments in transfer printing and solution-based methods now allow these materials to be incorporated into large-area electronics1,2,3,4,5,6. Similar efforts are now being devoted to making the integration of graphene into devices technologically feasible7,8,9,10. Here, we report a solution-based method that allows uniform and controllable deposition of reduced graphene oxide thin films with thicknesses ranging from a single monolayer to several layers over large areas. The opto-electronic properties can thus be tuned over several orders of magnitude, making them potentially useful for flexible and transparent semiconductors or semi-metals. The thinnest films exhibit graphene-like ambipolar transistor characteristics, whereas thicker films behave as graphite-like semi-metals. Collectively, our deposition method could represent a route for translating the interesting fundamental properties of graphene into technologically viable devices.