Steve Lipa

Bio: Steve Lipa is an academic researcher from North Carolina State University. The author has contributed to research in topics: Physical design & Multi-core processor. The author has an hindex of 6, co-authored 18 publications receiving 590 citations.

Rotary traveling-wave oscillator arrays: a new clock technology

Abstract: Rotary traveling-wave oscillators (RTWOs) represent a new transmission-line approach to gigahertz-rate clock generation. Using the inherently stable LC characteristics of on-chip VLSI interconnect, the clock distribution network becomes a low-impedance distributed oscillator. The RTWO operates by creating a rotating traveling wave within a closed-loop differential transmission line. Distributed CMOS inverters serve as both transmission-line amplifiers and latches to power the oscillation and ensure rotational lock. Load capacitance is absorbed into the transmission-line constants whereby energy is recirculated giving an adiabatic quality. Unusually for an LC oscillator, multiphase (360/spl deg/) square waves are produced directly. RTWO structures are compact and can be wired together to form rotary oscillator arrays (ROAs) to distribute a phase-locked clock over a large chip. The principle is scalable to very high clock frequencies. Issues related to interconnect and field coupling dominate the design process for RTWOs. Taking precautions to avoid unwanted signal couplings, the rise and fall times of 20 ps, suggested by simulation, may be realized at low power consumption. Experimental results of the 0.25-/spl mu/m CMOS test chip with 950-MHz and 3.4-GHz rings are presented, indicating 5,5-ps jitter and 34-dB power supply rejection ratio (PSRR). Design errors in the test chip precluded meaningful rise and fall time measurements.

Design and CAD for 3D integrated circuits

Abstract: High density through silicon vias (TSV) can be used to build 3DICs that enable unique applications in computing, signal processing and memory intensive systems. This paper presents several case studies that are uniquely enhanced through 3D implementation, including a 3D CAM, an FFT processor, and a SAR processor. The CAD flow used to implement for these designs is described. 3DIC requires higher fidelity thermal modeling than 2DIC design. The rationale for this requirement is established and a possible solution is presented.

Rationale for a 3D heterogeneous multi-core processor

Abstract: Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior.

A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integration

Abstract: In this paper we present a technique for implementing a fine-grain partitioned three-dimensional SAR DSP system using 3D placement of standard cells where only one of the 3D tiers is clocked to reduce clock power. We show how this technique was used to build the first fine-grain partitioned 3D integrated system to be demonstrated with silicon measurements in the literature, which is an ultra efficient floating-point synthetic aperture radar (SAR) DSP processing unit. The processing unit was fabricated in two tiers of GlobalFoundries, 1.5 V 130nm process that were 3D stacked face-to-face by Tezzaron. After fabrication the test chip was measured to consume 4.14 mW of power while running at 40 MHz operating for an operating efficiency of 10.35 mW/GFlop.

The properties and applications of nanodiamonds

Abstract: Nanodiamonds have excellent mechanical and optical properties, high surface areas and tunable surface structures. They are also non-toxic, which makes them well suited to biomedical applications. Here we review the synthesis, structure, properties, surface chemistry and phase transformations of individual nanodiamonds and clusters of nanodiamonds. In particular we discuss the rational control of the mechanical, chemical, electronic and optical properties of nanodiamonds through surface doping, interior doping and the introduction of functional groups. These little gems have a wide range of potential applications in tribology, drug delivery, bioimaging and tissue engineering, and also as protein mimics and a filler material for nanocomposites.

High aspect ratio silicon etch: A review

Abstract: High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

System comprising a semiconductor device and structure

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Semiconductor device and structure

Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Method for fabrication of a semiconductor device and structure

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.