Steve Y-L Lin

Bio: Steve Y-L Lin is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: High-level synthesis & Microarchitecture. The author has an hindex of 3, co-authored 4 publications receiving 1779 citations.

High ― Level Synthesis: Introduction to Chip and System Design

Abstract: Preface. 1. Introduction. 2. Architectural Models in Synthesis. 3. Quality Measures. 4. Design Description Languages. 5. Design Representation and Transformations. 6. Partitioning. 7. Scheduling. 8. Allocation. 9. Design Methodology for High-Level Synthesis. Bibliography. Index.

Design Methodology for High-Level Synthesis

Abstract: In the previous chapters we have defined synthesis, presented target architectures and design-quality measures, discussed description languages and design representations and presented algorithms for partitioning, scheduling and allocation for synthesis on higher-than-logic abstraction levels. In this chapter we will combine those ideas into a design methodology for synthesis on system and chip levels. System-level synthesis takes a behavioral description of the complete system and generates another behavioral description of the same system in which each custom, semicustom or standard chip is described separately. Chip synthesis converts the behavioral description of each chip into a structural description with register-transfer (RT) components. We will discuss several alternatives for synthesis systems and the technical justification behind approaches taken in those alternatives. The work on design methodology is scarce and no high-level synthesis (HLS) systems are widely used in practice. In this chapter, we mainly discuss requirements for HLS systems and propose possible solutions, sometimes based on our own work but most often based on speculations on the nature of other work in industry and academia.

Architectural Models in Synthesis

Abstract: During the refinement of a given specification into a structural design of standard components, a designer first selects a design style and then defines a target architecture. We use the term design style to refer to the principal qualitative features of a design, such as prioritized interrupt, instruction buffer, snooping data cache, bus-oriented datapath, serial I/O, direct memory access, and others. A target architecture defines a design more precisely in terms of particular units, their parameters, and the connections among units. For example, a processor architecture would include the number of registers in the register file, the number of buses in the datapath, the number of pipeline stages, the number of status bits, the number of ways branching can occur, and so on.

Bus-invert coding for low-power I/O

Abstract: Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. >

Lambda Calculus with Types

Abstract: This handbook with exercises reveals in formalisms, hitherto mainly used for hardware and software design and verification, unexpected mathematical beauty. The lambda calculus forms a prototype universal programming language, which in its untyped version is related to Lisp, and was treated in the first author's classic The Lambda Calculus (1984). The formalism has since been extended with types and used in functional programming (Haskell, Clean) and proof assistants (Coq, Isabelle, HOL), used in designing and verifying IT products and mathematical proofs. In this book, the authors focus on three classes of typing for lambda terms: simple types, recursive types and intersection types. It is in these three formalisms of terms and types that the unexpected mathematical beauty is revealed. The treatment is authoritative and comprehensive, complemented by an exhaustive bibliography, and numerous exercises are provided to deepen the readers' understanding and increase their confidence using types.

Algorithms for VLSI Physical Design Automation

Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Bus-invert coding for low-powerI/O

Abstract: Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. >

A time-multiplexed FPGA

Abstract: This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 30 ns. Inactive memory is accessible as block RAM for applications. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware.