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Stuart Allen Berke

Bio: Stuart Allen Berke is an academic researcher. The author has contributed to research in topics: Memory controller & Memory segmentation. The author has an hindex of 1, co-authored 1 publications receiving 26 citations.

Papers
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Patent
09 Jul 2014
TL;DR: A dual-inline memory module includes a local memory and a non-volatile memory as mentioned in this paper, which stores data during normal operation of the dual inline memory module and can be used to set up the dual-inneme memory module in a new information handling system.
Abstract: A dual inline memory module includes a local memory and a non-volatile memory. The local memory stores data during normal operation of the dual inline memory module. The non-volatile memory includes a first portion and a second portion. The first portion stores the data located in the local memory in response to a power failure of an information handling system in communication with the dual inline memory module. The second portion stores configuration information for the dual inline memory module. The configuration information is utilized to set up the dual inline memory module in a new information handling system.

26 citations


Cited by
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Patent
08 Feb 2016
TL;DR: In this paper, a storage device is provided which includes a nonvolatile memory and a temperature sensor, which is configured to detect a temperature of the storage device and to output temperature information.
Abstract: A storage device is provided which includes a nonvolatile memory and a temperature sensor. The temperature sensor is configured to detect a temperature of the storage device. The temperature sensor is configured to output temperature information. The storage device includes a memory controller. The memory controller is configured to access the nonvolatile memory in response to a request of an external host device. The memory controller is configured to obtain the temperature information from the temperature sensor according to a first period in a first mode. The temperature sensor is configured to obtain the temperature information from the temperature sensor according to a second period in a second mode. The second period is shorter than the first period.

35 citations

Patent
22 Dec 2014
TL;DR: In this paper, the memory controller logic configures non-volatile memory into a plurality of partitions at least in part based on one or more attributes, each of which includes at least one similar attribute from the attributes.
Abstract: Methods and apparatus to allocating and/or configuring persistent memory are described. In an embodiment, memory controller logic configures non-volatile memory into a plurality of partitions at least in part based on one or more attributes. One or more volumes (visible to an application or operating system) are formed from one or more of the plurality of partitions. Each of the one or more volumes includes one or more of the plurality of partitions having at least one similar attribute from the one or more attributes. In another embodiment, memory controller logic configures a Non-Volatile Memory (NVM) Dual Inline Memory Module (DIMM) into a persistent region and a volatile region. Other embodiments are also disclosed and claimed.

26 citations

Patent
19 Dec 2014
TL;DR: In this article, the authors describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non volatile memory.
Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

16 citations

Patent
04 Apr 2016
TL;DR: In this paper, the authors propose a method to encode and decode raw data by decomposing the uncoded data into a plurality of data vectors, mapping each of the plurality of vectors to a bit marker, and storing the bit marker in a memory.
Abstract: System and method to encode and decode raw data. The method to encode includes receiving a block of uncoded data, decomposing the block of uncoded data into a plurality of data vectors, mapping each of the plurality of data vectors to a bit marker; and storing the bit marker in a memory to produce an encoded representation of the uncoded data. Encoding may further include decomposing the block of uncoded data into default data and non-default data, and mapping only the non-default data. In some embodiments, bit markers may include a seed value and replication rule, or a fractalized pattern.

11 citations

Patent
30 Sep 2016
TL;DR: In this article, a power supply that, in the event of a power failure, triggers a hardware non-maskable interrupt (NMI) and sustains power to the CPU to allow cached data to be saved to non-volatile memory locations in the NVDIMM before the computer system completely powers down.
Abstract: A computer system includes a dual in-line memory module (DIMM), such as a registered DIMM (RDIMM), and a non-volatile DIMM (NVDIMM). A central processing unit (CPU) of the computer system has internal cache memory locations for caching data for the DIMM and NVDIMM. A memory type range register (MTTR) of the CPU is set for write-back cache strategy for a range of memory locations in the DIMM and NVDIMM. The computer system includes a power supply that, in the event of a power failure, triggers a hardware non-maskable interrupt (NMI) and sustains power to the CPU to allow cached data to be saved to non-volatile memory locations in the NVDIMM before the computer system completely powers down.

9 citations