Subadra Murugan

Bio: Subadra Murugan is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Overhead (computing) & Electronic nose. The author has an hindex of 2, co-authored 2 publications receiving 32 citations.

Shakti-T: A RISC-V Processor with Light Weight Security Extensions

Abstract: With increased usage of compute cores for sensitive applications, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hardware framework for handling spatial and temporal memory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-architecture with an enhanced application binary interface that enables software layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the design through a VLSI CAD design flow. The proposed processor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 flip flops on an FPGA, without affecting the critical path delay of the processor.

ELENA: A low-cost portable electronic nose for alcohol characterization

Abstract: While detection of alcohols in trace quantities is useful in a variety of commercial, industrial, environmental and defense applications, it plays a very crucial role in biomedical applications. Concentration of alcohols of as low as 0.4% methanol in 40% ethanol in blood is considered to be lethal and can lead to serious health issues. Developing a low cost highly accurate and a portable device to detect alcohol concentrations has always remained a challenge. Modern day solutions either require sophisticated equipment or unable to estimate concentrations with high accuracy. This work focuses on determination of alcohols in different concentrations in trace quantities using an electronic nose technology — ELENA. It is a portable device which consists of an array of sensors inside a sensor chamber, with a pin hole inlet, whose output is connected to a data acquisition and pattern recognition system. The pattern recognition system utilizes a neural network to estimate the concentration of alcohol in the provided sample. The entire setup has been validated for sensitivity and specificity.

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product

Abstract: The open source RISC-V ISA has been quickly gaining momentum. This paper presents Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it features custom extensions to arithmetic operation, bit manipulation, load and store, TLB and cache operations. It also implements the 0.7.1 stable release of RISC-V vector extension specification for high efficiency vector processing. Xuantie-910 supports multi-core multi-cluster SMP with cache coherence. Each cluster contains 1 to 4 core(s) capable of booting the Linux operating system. Each single core utilizes the state-of-the-art 12-stage deep pipeline, out-of-order, multi-issue superscalar architecture, achieving a maximum clock frequency of 2.5 GHz in the typical process, voltage and temperature condition in a TSMC 12nm FinFET process technology. Each single core with the vector execution unit costs an area of 0.8 mm2 (excluding the L2 cache). The toolchain is enhanced significantly to support the vector extension and custom extensions. Through hardware and toolchain co-optimization, to date Xuantie-910 delivers the highest performance (in terms of IPC, speed, and power efficiency) for a number of industrial control flow and data computing benchmarks, when compared with its predecessors in the RISC-V family. Xuantie-910 FPGA implementation has been deployed in the data centers of Alibaba Cloud, for application-specific acceleration (e.g., blockchain transaction). The ASIC deployment at low-cost SoC applications, such as IoT endpoints and edge computing, is planned to facilitate Alibaba's end-to-end and cloud-to-edge computing infrastructure.

Development of compact electronic noses: a review

Abstract: An electronic nose (e-nose) is a measuring instrument that mimics human olfaction and outputs ‘fingerprint’ information of mixed gases or odors. Generally speaking, an e-nose is mainly composed of two parts: a gas sensing system (gas sensor arrays, gas transmission paths) and an information processing system (microprocessor and related hardware, pattern recognition algorithms). It has been more than 30 years since the e-nose concept was introduced in the 1980s. Since then, e-noses have evolved from being large in size, expensive, and power-hungry instruments to portable, low cost devices with low power consumption. This paper reviews the development of compact e-nose design and calculation over the last few decades, and discusses possible future trends. Regarding the compact e-nose design, which is related to its size and weight, this paper mainly summarizes the development of sensor array design, hardware circuit design, gas path (i.e. the path through which the mixed gases to be measured flow inside the e-nose system) and sampling design, as well as portable design. For the compact e-nose calculation, which is directly related to its rapidity of detection, this review focuses on the development of on-chip calculation and wireless computing. The future trends of compact e-noses include the integration with the internet of things, wearable e-noses, and mobile e-nose systems.

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip

Abstract: Securing thousands of connected, resource-constrained computing devices is a major challenge nowadays. Adding to the challenge, third party service providers need regular access to the system. To ensure the integrity of the system and authenticity of the software vendor, secure boot is supported by several commercial processors. However, the existing solutions are either complex, or have been compromised by determined attackers. In this scenario, open-source secure computing architectures are poised to play an important role for designers and white hat attackers. In this manuscript, we propose a lightweight hardware-based secure boot architecture. The architecture uses efficient implementation of Elliptic Curve Digital Signature Algorithm (ECDSA), Secure Hash Algorithm 3 (SHA3) hashing algorithm and Direct Memory Access (DMA). In addition, the architecture includes Key Management Unit, which incorporates an optimized Physical Unclonable Function (PUF) for providing keys to the security blocks of the System on Chip (SoC), among which, secure boot and remote attestation. We demonstrated the framework on RISC-V based SoC. Detailed analysis of performance and security for the platform is presented.

SHAKTI-MS: a RISC-V processor for memory safety in C

Abstract: In this era of IoT devices, security is very often traded off for smaller device footprint and low power consumption. Considering the exponentially growing security threats of IoT and cyber-physical systems, it is important that these devices have built-in features that enhance security. In this paper, we present Shakti-MS, a lightweight RISC-V processor with built-in support for both temporal and spatial memory protection. At run time, Shakti-MS can detect and stymie memory misuse in C and C++ programs, with minimum runtime overheads. The solution uses a novel implementation of fat-pointers to efficiently detect misuse of pointers at runtime. Our proposal is to use stack-based cookies for crafting fat-pointers instead of having object-based identifiers. We store the fat-pointer on the stack, which eliminates the use of shadow memory space, or any table to store the pointer metadata. This reduces the storage overheads by a great extent. The cookie also helps to preserve control flow of the program by ensuring that the return address never gets modified by vulnerabilities like buffer overflows. Shakti-MS introduces new instructions in the microprocessor hardware, and also a modified compiler that automatically inserts these new instructions to enable memory protection. This co-design approach is intended to reduce runtime and area overheads, and also provides an end-to-end solution. The hardware has an area overhead of 700 LUTs on a Xilinx Virtex Ultrascale FPGA and 4100 cells on an open 55nm technology node. The clock frequency of the processor is not affected by the security extensions, while there is a marginal increase in the code size by 11% with an average runtime overhead of 13%.

Stack Redundancy to Thwart Return Oriented Programming in Embedded Systems

Abstract: With the emergence of Internet of Things, embedded devices are increasingly the target of software attacks. The aim of these attacks is to maliciously modify the behavior of the software being executed by the device. The work presented in this letter has been developed for the Cyber Security Awareness Week Embedded Security Challenge. This contest focuses on memory corruption issues, such as stack overflow vulnerabilities. These low level vulnerabilities are the result of code errors. Once exploited, they allow an attacker to write arbitrary data in memory without limitations. We detail in this letter a hardware-based countermeasure against return address corruption in the processor stack. First, several exploitation techniques targeting stack return addresses are discussed, whereas a lightweight hardware countermeasure is proposed and validated on the OpenRISC core. The countermeasure presented follows the shadow stack concept with a minimal hardware modification of the targeted core and an easy integration at the application level.