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Subhra Chakraborty

Bio: Subhra Chakraborty is an academic researcher from Birla Institute of Technology, Mesra. The author has contributed to research in topics: Open-loop gain & Operational amplifier. The author has an hindex of 4, co-authored 10 publications receiving 45 citations.

Papers
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Journal ArticleDOI
TL;DR: The proposed CMOS Low Noise amplifier has been verified through cadence spectre RF simulation in standard UMC 90 nm CMOS process and designed by cascoding of two transistors; that is the common source transistor drives a common gate transistor.
Abstract: In this paper a 2.45 GHz narrowband low noise amplifier (LNA) for wireless communication system is enunciated. The proposed CMOS Low Noise amplifier has been verified through cadence spectre RF simulation in standard UMC 90 nm CMOS process. The proposed LNA is designed by cascoding of two transistors; that is the common source transistor drives a common gate transistor. To achieve better power gain along with low noise figure, cascoding of two transistor and source degeneration technique is used and for low power consumption, the MOS transistors are biased in subthreshold region. At 2.45 GHz frequency, it exhibits power gain 31.53 dB. The S11, S22 and S12 of the circuit is ź9.14, ź9.22 and ź38.03 dB respectively. The 1 dB compression point of the circuit is ź16.89 dBm and IIP3 is ź5.70 dBm. The noise figure is 2.34 dB, input/output match of ź9.14 dB/ź9.22 dB and power consumption 8.5 mW at 1.2 V.

14 citations

Proceedings ArticleDOI
23 Apr 2015
TL;DR: A new CMOS operational amplifier using a Darlington pair based gain boosted technique has been enunciated and shows high gain as well as high UGB using capacitor compensation technique and proper biasing circuit.
Abstract: In this paper a new CMOS operational amplifier using a Darlington pair based gain boosted technique has been enunciated. The proposed Opamp shows high gain as well as high UGB using capacitor compensation technique and proper biasing circuit. It is operated on rail to rail power supply of ±900mV. This amplifier is highly useful for wireless communications due to low power consumption, high bandwidth, high gain and high noise immunity. The designed operational amplifier gain is 89dB, bandwidth is 4.40 GHz and phase margin is 67O, and slew rate is 991.6V/μS. This circuit is designed using Cadence analog & digital system design tools of gpdk45nm technology.

9 citations

Journal ArticleDOI
TL;DR: An ultra high gain two stage CMOS Operational Amplifier which is designed using self-cascoding and positive feedback technique in order to provide gain enhancement is presented.
Abstract: This paper presents an ultra high gain two stage CMOS Operational Amplifier which is designed using self-cascoding and positive feedback technique in order to provide gain enhancement. By comparing the circuit with other designed circuits it has been shown that applying positive feedback increases the gain of the Op-Amp without affecting other properties of the amplifier. The proposed circuit is designed in 45 nm technology using Cadence Virtuoso Analog Design Environment tool at ±1 V supply. The Op-Amp is designed to achieve a high gain of 141 dB while maintaining a UGB of 101 MHz and phase margin of 60°. The simulation results conforms the estimated theoretical improvements. The dependence of various properties such as slew rate, UGB, settling time and phase margin of the designed Op-Amp on compensating capacitor CC has also been analyzed in this paper. Finally, the simulation results have been compared with a previously reported Op-Amp utilizing positive feedback technique.

9 citations

01 Jan 2015
TL;DR: In this paper, the Darlington pair and internal circuit biasing technique is used for enhancing the slew rate as well as gain and unity gain bandwidth in the standard 45nm CMOS Op-Amp.
Abstract: In this paper the Darlington pair and internal circuit biasing technique is used for the enhancing the slew rate as well as gain and unity gain bandwidth. The proposed CMOS Op-Amp has been verified through Cadence Analog Design Environment with spectre simulator in the standard 45nm CMOS process. In this proposed circuit the gain stage is divided in two parts, first is modified gain stage and second one is Darlington pair stage. The effects of both the modified gain stage and Darlington stage currents are considered in this circuit and a simple analytical expression is given in terms of the load and compensation capacitors. The new scheme allows the slew rate to be increased with only a small increase in static power consumption. At the dc power dissipation of 0.76 mW, the proposed circuit achieves a slew rate of 2791V/μs, gain of 70 dB and unity gain bandwidth of 1.74 GHz. Keyword: slew rate, darlington pair, op amp, UGB, load capacitor, compensation capacitor.

5 citations

Proceedings ArticleDOI
23 Apr 2015
TL;DR: A compact low power temperature sensor that doesn't require any BJT and it is based on temperature dependency of threshold voltage of MOSFETs is introduced in this paper.
Abstract: A compact low power temperature sensor has been introduced in this paper. The proposed temperature sensor doesn't require any BJT and it is based on temperature dependency of threshold voltage of MOSFETs. The sensor is designed using seven transistors which are operated in sub-threshold region. The circuit has been simulated in Cadence with UMC90nm library using a power supply of ±0.5V. The circuit linearly senses between the temperature of −25°C to +65°C. The designed circuit shows an inaccuracy of ±0.85°C while consuming just 1.37nW.

3 citations


Cited by
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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.

1,038 citations

Book ChapterDOI
01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

207 citations

Journal ArticleDOI
TL;DR: An approach for efficient cluster head selection namely Energy Dependent Cluster Formation in Heterogeneous Wireless Sensor Network (EDCF) to enhance the lifespan of network is proposed.
Abstract: The applications of Wireless Sensor Network is increasing rapidly in almost every domain. So, the limited node’s battery life in the network should be utilized efficiently. Various approaches have been proposed earlier to lessen the usage of energy in the network and to enhance the network lifespan. In this paper we are proposing an approach for efficient cluster head selection namely Energy Dependent Cluster Formation in Heterogeneous Wireless Sensor Network (EDCF) to enhance the lifespan of network. The simulation of the proposed EDCF technique is performed in MATLAB simulator and to measure its performance the comparison is performed with various existing protocols. The proposed EDCF protocol has shown the enhancement in the lifespan of the network as compared to the previous clustering approaches.

47 citations

Journal ArticleDOI
TL;DR: In this article, a single-stage class AB bulk-driven amplifier operating in weak inversion region is proposed, which benefits from an improved high input swing structure using quasi-floating-gate technique.
Abstract: In this paper, a single-stage class AB bulk-driven amplifier operating in weak inversion region is proposed. The presented amplifier benefits from an improved high input swing structure using quasi-floating-gate technique. The composite transistors and recycling configuration used at the input stage enable the input differential pair to operate under low supply voltages with larger transconductance as compared to the conventional models at no expense of power budget. The circuit is designed in 0.18 µm CMOS technology and simulation results show 61.5 dB low frequency gain with the gain bandwidth of 30.15 kHz and 55.3 V/ms average slew rate. The total current of 275 nA and 0.6 V supply voltage make the proposed amplifier a suitable choice for ultra-low-power applications.

18 citations

Proceedings ArticleDOI
01 Jan 2016
TL;DR: In this paper, a single-ended LNA with high gain and minimum noise performance for Global Positioning System (GPS) application is enunciated and simulated via cadence using UMC 90 nm library.
Abstract: This paper is enunciated a LNA with high gain and minimum noise performance for Global Positioning System (GPS) application. The CMOS Low Noise amplifier implementation is designed and simulated via cadence using UMC 90 nm library. The topology is single ended LNAs designed which uses cascaded transistor for isolation; the common source transistor is driven by common gate transistor. To have objective for good voltage gain with minimum noise figure, cascoding input matching is done using source degeneration technique. Transistors are operated in sub threshold region. At 1.57 GHz frequency, parameters like power gain, input matching, output matching, isolation, stability are examined by S-parameters. The voltage gain of LNA is 31 dB. The noise figure is 0.533 dB, 1dB compression point is −16.95 dBm and IIP3 is 2.91 dBm. The LNA is having power consumption as 8.7 mW for 1.5 V supply.

11 citations