scispace - formally typeset
Search or ask a question
Author

Suchismita De

Bio: Suchismita De is an academic researcher from University of Calcutta. The author has contributed to research in topics: NMOS logic & CMOS. The author has an hindex of 2, co-authored 5 publications receiving 10 citations.
Topics: NMOS logic, CMOS, Rise time, Ring oscillator, Inverter

Papers
More filters
Journal ArticleDOI
TL;DR: In this article, the influence of the sidewall spacers on the analog performance of InGaAs nMOSFETs at channel lengths of 32 and 22nm was investigated in analog domain.
Abstract: In this paper, we report, for the first time, the influence of the sidewall spacers (SWS) on the analog performance of InGaAs nMOSFETs at channel lengths of 32 and 22 nm. The study is further extended to the circuit level in which the impact of spacer layer on hybrid CMOSFETs comprising InGaAs nMOSFETs and Si pMOSFETs is thoroughly investigated in analog domain. Using extensive numerical analysis we study the impact of SWS layers on various device parameters e.g., transconductance (gm), transconductance efficiency (gm/ID), output conductance (gd) and intrinsic gain (gm/gd) related to analog applications. Then, the hybrid CMOS current source load amplifier is studied in terms of voltage gain, total capacitance (CTotal) and gain bandwidth product (GBW). The simulation scheme is validated with reported experimental data in the literature. Our findings reveal that all the parameters at the device level, except gd exhibit improved performance for higher value of spacer k. On the contrary, gd decreases with reduced k-value and becomes weakly sensitive to the variation in spacer length (Lsp), for the InGaAs nMOS device having channel lengths (Lg) of 22 and 32 nm. At the circuit level, for the hybrid CMOS amplifier, we found that the dc-gain and CTotal exhibit larger value for higher value of Lsp, while GBW shows higher value for reduced Lsp. Our investigation suggests that improved analog performance of InGaAs nMOSFETs with suitable SWS engineering may be achieved at more advanced technology nodes.

5 citations

Journal ArticleDOI
TL;DR: In this article, the digital performance of 30-nm hybrid CMOS inverters comprising Si p-MOSFETs and In0.70Ga0.30As n-mOSFets in terms of rise time (tr), fall time (tf), propagation delay (td), noise margins high (NMH) and low (NML) of an inverter, and also the oscillation frequency (fosc) of a ring oscillator with and without considering NBTI effects was analyzed.

5 citations

Journal ArticleDOI
TL;DR: In this paper, the influence of negative bias temperature temperature instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, was investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and oscillators with reference to frequency of oscillations.
Abstract: This paper reports, for the first time, the influence of pMOS-negative-bias-temperature-instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, followed by a three-stage-ring-oscillator. The logic performance of an inverter is investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and that for oscillators with reference to frequency of oscillations (fosc). Obtained results show percentage degradation values of 15.38%, 42.90%, 34.09%, and 23.44% for NMH, tr, td, and fosc, respectively, for a stress time of 10 s. It is also found that the oscillation frequency of the ring oscillator degrades ~ 30% for the stress time of 10,000 s compared to without NBTI value.

3 citations

Journal ArticleDOI
TL;DR: In this article, the authors investigate the logic performance of hybrid (H) CMOS devices comprising Ge p-MOSFETs and Si n -MOSFLETs in terms of rise time, fall time, propagation delay and noise margins using extensive numerical device simulation.

2 citations

Book ChapterDOI
01 Jan 2021
TL;DR: In this paper, a comparative analysis is carried out to study the digital circuit behavior of hybrid p-Ge/n-Si CMOSFETs, p-Si/N-InGaAs CMOSFsETs as well as conventional Si CMOS devices at channel length of 60, 30, and 20 nm.
Abstract: A comparative analysis is carried out to study the digital circuit behavior of hybrid p-Ge/n-Si CMOSFETs, p-Si/n-InGaAs CMOSFETs as well as conventional Si CMOS devices at channel length of 60, 30, and 20 nm. Extensive numerical investigation is used to investigate the performance of the different inverter circuits in terms of noise margin low and high, rise and fall times alongside propagation delay. Our studies show that hybrid CMOSFET comprising Si nMOS and Ge pMOS devices performs the best with respect to noise margin high (NMH), noise margin low (NML), and rise time (tr) compared to the hybrid CMOSET comprising InGaAs nMOS and Si pMOS devices and the conventional CMOSFET. However, n-InGaAs/p-Si CMOSFET yields the lowest value of fall time (tf) and time delay per inverter (td) in relation to the values found in other two inverters. Our investigation reveals that all the time parameters for both hybrid CMOSFETs show reduced value compared to the conventional Si counterpart while noise margins show improvement for Si CMOSFETs.

Cited by
More filters
Journal ArticleDOI
TL;DR: In this article , the performance of gate all around (GAA) nanosheet FETs with different geometrical variations of the gate-all-around FET are computationally examined.

8 citations

Journal ArticleDOI
TL;DR: In this paper, the authors proposed a method for supporting research at the King Abdullah University of Science and Technology (KAUST), which was supported by K.F. and A.S.A.E.
Abstract: E.F. and A.S.A. contributed equally to this work. This research was supported by King Abdullah University of Science and Technology (KAUST).

6 citations

Journal ArticleDOI
TL;DR: In this paper, the influence of negative bias temperature temperature instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, was investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and oscillators with reference to frequency of oscillations.
Abstract: This paper reports, for the first time, the influence of pMOS-negative-bias-temperature-instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, followed by a three-stage-ring-oscillator. The logic performance of an inverter is investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and that for oscillators with reference to frequency of oscillations (fosc). Obtained results show percentage degradation values of 15.38%, 42.90%, 34.09%, and 23.44% for NMH, tr, td, and fosc, respectively, for a stress time of 10 s. It is also found that the oscillation frequency of the ring oscillator degrades ~ 30% for the stress time of 10,000 s compared to without NBTI value.

3 citations