Suchismita Tewari

Bio: Suchismita Tewari is an academic researcher from University of Calcutta. The author has contributed to research in topics: CMOS & MOSFET. The author has an hindex of 6, co-authored 27 publications receiving 132 citations.

Study of InGaAs-Channel MOSFETs for Analog/Mixed-Signal System-on-Chip Applications

Abstract: MOSFETs with InGaAs in the channel show great promise for high-performance digital applications owing to enhanced electron mobility. In this letter, the analog performance is reported for the first time for an inversion-type enhancement-mode InGaAs-channel MOSFET. With the help of a device simulator, the device parameters for analog applications such as transconductance , transconductance-to-drain-current ratio , drain resistance , intrinsic gain, and unity-gain cutoff frequency are studied for such a device and compared with those for a similarly sized MOSFET. Our results show that InGaAs devices outperform their Si counterparts for analog applications.

Impact of Different Barrier Layers and Indium Content of the Channel on the Analog Performance of InGaAs MOSFETs

Abstract: A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices.

Impact of a Spacer Layer on the Analog Performance of Asymmetric InP/InGaAs nMOSFETs

Abstract: An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths ( $L_{g}$ ) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental characteristics reported in the literature. Our investigations reveal that device parameters such as transconductance $g_{m}$ , transconductance generation factor, and voltage gain $A_{v}$ exhibit significant improvement when a spacer of high dielectric constant $k$ , such as 25, and small length $L_{\textrm {sp}}$ , such as 5 nm, are used for both $L_{g}= 20$ and 30 nm. On the contrary, the output conductance and unity gain cutoff frequency are found to reduce and increase, respectively, with lower $k$ and larger $L_{\textrm {sp}}$ of the spacer. Our studies suggest that improved analog performance of In-rich asymmetric InGaAs MOSFETs can be achieved by spacer layer engineering at advanced technology nodes.

Optimization of Hetero-Gate-Dielectric Tunnel FET for Label-Free Detection and Identification of Biomolecules

Abstract: In this article, for the first time, the performance of a double-hetero-gated-dielectric-modulated tunnel FET (DHGDM-TFET) biosensor device, having channel length ( ${L}_{\text{ch}}$ ) of 50 nm, is thoroughly investigated in terms of threshold voltage- ( ${V}_{\text {TH}}$ -), subthreshold swing- (SS-), ON-current- ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ -), and OFF-current- ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ -) sensitivity parameters, in order to find its suitability in successful detection and identification of different biomolecules. The investigation is further extended to the optimization of the proposed sensor device, against cavity length ( ${L}_{\text {Cavity}}$ ) and misalignment effect between the cavity and high- ${k}$ dielectric, underneath the cavity of the sensor device. It is found that our proposed biosensor device works at its optimum with ${L}_{\text {Cavity}} =10$ nm, while the cavity is perfectly aligned with the underneath high- ${k}$ of the device. Furthermore, a comparison of our proposed device is performed against its equivalent high- ${k}$ only and SiO2 only TFET-based biosensors. For each aforementioned sensitivity parameter, it is found that our proposed DHGDM-TFET biosensor device outperforms the rest two devices, proving the superiority in sensing action.

Dual-Metal Double-Gate with Low-k/High-k Oxide Stack Junctionless MOSFET for a Wide Range of Protein Detection: a Fully Electrostatic Based Numerical Approach

Abstract: We investigate the performance of a dielectric modulated dual-metal double-gate with low-k/high-k oxide stack junctionless MOSFET (DM-DG-LK/HK-S JL-MOSFET) based sensor device for successful detection of different protein molecules in dry environment condition, in terms of the absolute and relative change in the threshold voltage (Vth), called Vth-responsivity and Vth-sensitivity, respectively. The influence of work-function difference of the DM-gate along with the position of cavity containing biomolecules, followed by the impact of cavity dimension, on the sensing metrics, have been thoroughly inspected. Furthermore, the optimization of cavity dimension, along with proper DM-gate work-function engineering is done for the wide range of protein detection. For the sensor device, having channel length (Lch) of 1 μm, this optimum cavity dimension is found to be (400 nm × 10 nm). It is observed that, the device with Lch = 1 μm exhibits superior sensing performance when, along with the source-side cavity, the drain-side gate metal has got higher work-function than the source-side gate metal (i.e., ɸM2 > ɸM1), compared to the case when ɸM1 > ɸM2 and the cavity is located near the drain-side. Respective performance enhancements, in terms of percentage improvement of Vth-responsivity and Vth-sensitivity, are found to be 250% and 263% for the detection of Staphylococcal nuclease. Similar trend is found for the sensor devices with Lch = 50 nm.

A Novel PNPN-Like Z-Shaped Tunnel Field- Effect Transistor With Improved Ambipolar Behavior and RF Performance

Abstract: To suppress the ambipolar behavior and improve RF performance in tunnel field-effect transistors (TFETs), a Z-shaped (ZS)-TFET is proposed. The proposed ZS-TFET is more scalable than other vertical band-to-band-based TFETs and provides higher ON-state current ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}$ ), larger ON/OFF current ratio ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}/{I} _{ {\mathrm{\scriptscriptstyle OFF}}}$ ) and lower subthreshold swing compared to conventional TFETs. These advantages stem from the tunneling junction in the ZS-TFET being perpendicular to the channel direction, which facilitates the formation of a relatively large tunneling junction area. The ZS body makes use of both vertical and horizontal fields while suppressing the lateral parasitic tunneling current. In addition, by using a ZS gate in the proposed device, the energy band diagram near the source is modulated to create an N+ source pocket which creates a downward band bending of the potential, similar to PNPN-like structures. Finally, the proposed structure significantly improves the analog/RF figure-of-merit.

Performance Evaluation of Dielectrically Modulated Extended Gate Single Cavity InGaAs/Si HTFET Based Label-Free Biosensor Considering Non-Ideal Issues

Abstract: The dielectrically modulated heterostructure TFET based nanocavity embedded label-free biosensors are emerging as low power, highly sensitive bio-analyte detectors. High sensitivity and fast detection of biomolecules are still a challenge for researchers. In this article, single cavity dual-material extended gate heterostructure (III-V) TFET (SC-DM-EG HTFET) based dielectrically modulated label-free biosensor is proposed; which promises higher sensitivity and better device performances such as, ON current, $\text{I}_{ON}/\text{I}_{OFF}$ ratio, subthreshold swing (SS); compared with single cavity dual-material heterostructure TFET (SC-DM HTFET), dual cavity dual-material heterostructure TFET (DC-DM HTFET), as well as, previously proposed FET based biosensors. 2D numerical simulation of the biosensors was performed with SILVACO ATLAS 2D simulation software. III-V heterostructure (InGaAs/Si) and extended gate geometry provide increased tunneling probability, improved gate control, high $\text{I}_{ON}/\text{I}_{OFF}$ ratio, and ultra-high sensitivity, compared to IV-IV heterostructure biosensors. The sensitivities of the biosensors are analyzed for both neutral and charged biomolecules, with dielectric constants $\text{K}=5$ ,7,10,12. Effect of non-ideal issues on sensitivity, such as temperature fluctuation, steric hindrance are also studied for the biosensors mentioned above. Benchmarking is done to provide a quantitative comparison of the proposed biosensor with published literature. A maximum sensitivity of $1.3\times 10^{8}$ , along with the $\text{I}_{ON}/\text{I}_{OFF}$ ratio of $2\times 10^{12}$ and SS of 25.4 mV/V is noticed in SC-DM-EG HTFET for the dielectric constant of $\text{K}=12$ in a completely filled cavity of neutral biomolecules.

Impact of Different Barrier Layers and Indium Content of the Channel on the Analog Performance of InGaAs MOSFETs

Abstract: A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices.

Impact of barrier thickness on Analog, RF and Linearity performance of nanoscale DG heterostructure MOSFET

Abstract: In this work, we have analyzed the Analog, RF and Linearity performance of InP/InGaAs hetero-junction MOSFET using TCAD device simulation. A detailed investigation of the impact of barrier layer thickness on different Analog, RF and Linearity performance of an InGaAs/InP heterostructure DG MOSFET is carried out. A thorough analysis of the key figure-of-merits such as transconductance ( g m ), Output resistance ( R o ), gate capacitance, cutoff frequency ( f T ), maximum frequency of oscillation ( f max ), VIP2, VIP3, IIP3, IMD3 and 1 dB compression point are performed for various barrier thickness ranging from 1 nm to 4 nm. From the simulation results it is observed that performance of nanoscale DG heterostructure MOSFET is affected by the variation of barrier thickness of the device.