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Sudhakar M. Reddy

Other affiliations: University of Freiburg, Bell Labs, Iowa State University  ...read more
Bio: Sudhakar M. Reddy is an academic researcher from University of Iowa. The author has contributed to research in topics: Automatic test pattern generation & Fault coverage. The author has an hindex of 61, co-authored 685 publications receiving 15481 citations. Previous affiliations of Sudhakar M. Reddy include University of Freiburg & Bell Labs.


Papers
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Journal ArticleDOI
TL;DR: Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect pathdelay faults are proposed.
Abstract: Correct operation of a logic circuit requires propagation delays of all paths in the circuit to be smaller than the intended "clock interval." Random or deterministic tests, conducted at the normal clocking rate, can be used to insure that path delays in manufactured circuits meet the specifications. Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect path delay faults are proposed. The results can be used to determine the test length for a desired confidence level in testing a path fault when random tests are used, and to generate a test set for a list of delay faults when deterministic tests are used.

554 citations

Journal ArticleDOI
TL;DR: Heuristics with good performance bounds can be derived for combinational circuits tested using built-in self-test (BIST) and considerable reduction in power dissipation can be obtained using the proposed techniques.
Abstract: Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.

338 citations

Journal ArticleDOI
TL;DR: Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCas-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposedHeuristics.
Abstract: Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >

332 citations

Journal ArticleDOI
TL;DR: A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties of "easily testable networks".
Abstract: Desirable properties of "easily testable networks" are given. A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties. If only permanent stuck-at-0 (s-a-0) or stuck-at-1 (s-a-1) faults occur in a single AND gate or only a single EXCLUSIVE-OR gate is faulty, the following results are derived on fault detecting test sets for the proposed networks: 1) only (n/4) tests, independent of the function being realized, are required if the primary inputs are fault-free; 2) only 2n, additional inputs (which depend on the function realized) are required if the primary inputs can be faulty, where n, is the number of variables appearing in even number of product terms in the Reed-Muller canonical expansion of the function; and 3) the additional 2ne inputs are not required if the network is provided with an observable point at the output of an extra AND gate.

278 citations

Proceedings ArticleDOI
01 Oct 2006
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Abstract: When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

247 citations


Cited by
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[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

Book
01 Feb 1996

3,617 citations

Journal ArticleDOI
TL;DR: It is shown that choosing a transmission order for the digits that is appropriate for the graph and the subcodes can give the code excellent burst-error correction abilities.
Abstract: A method is described for constructing long error-correcting codes from one or more shorter error-correcting codes, referred to as subcodes, and a bipartite graph. A graph is shown which specifies carefully chosen subsets of the digits of the new codes that must be codewords in one of the shorter subcodes. Lower bounds to the rate and the minimum distance of the new code are derived in terms of the parameters of the graph and the subeodes. Both the encoders and decoders proposed are shown to take advantage of the code's explicit decomposition into subcodes to decompose and simplify the associated computational processes. Bounds on the performance of two specific decoding algorithms are established, and the asymptotic growth of the complexity of decoding for two types of codes and decoders is analyzed. The proposed decoders are able to make effective use of probabilistic information supplied by the channel receiver, e.g., reliability information, without greatly increasing the number of computations required. It is shown that choosing a transmission order for the digits that is appropriate for the graph and the subcodes can give the code excellent burst-error correction abilities. The construction principles

3,246 citations

Journal ArticleDOI
Akers1
TL;DR: This paper describes a method for defining, analyzing, testing, and implementing large digital functions by means of a binary decision diagram that provides a complete, concise, "implementation-free" description of the digital functions involved.
Abstract: This paper describes a method for defining, analyzing, testing, and implementing large digital functions by means of a binary decision diagram. This diagram provides a complete, concise, "implementation-free" description of the digital functions involved. Methods are described for deriving these diagrams and examples are given for a number of basic combinational and sequential devices. Techniques are then outlined for using the diagrams to analyze the functions involved, for test generation, and for obtaining various implementations. It is shown that the diagrams are especially suited for processing by a computer. Finally, methods are described for introducing inversion and for directly "interconnecting" diagrams to define still larger functions. An example of the carry look-ahead adder is included.

1,813 citations