S
Sudheer Vemulapalli
Researcher at Texas Instruments
Publications - 23
Citations - 1928
Sudheer Vemulapalli is an academic researcher from Texas Instruments. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 14, co-authored 23 publications receiving 1887 citations.
Papers
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Journal ArticleDOI
All-digital PLL and transmitter for mobile phones
Robert Bogdan Staszewski,John Wallberg,Sameh S. Rezeq,Chih-Ming Hung,Oren Eliezer,Sudheer Vemulapalli,C. Fernando,Kenneth J. Maggio,Robert B. Staszewski,N. Barton,Meng-Chang Lee,P. Cruise,Manouchehr Entezari,Khurram Muhammad,Dirk Leipold +14 more
TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.
Journal ArticleDOI
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
TL;DR: A 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver.
Proceedings ArticleDOI
All-digital PLL and GSM/EDGE transmitter in 90nm CMOS
Robert Bogdan Staszewski,John Wallberg,Sameh S. Rezeq,Chih-Ming Hung,Oren Eliezer,Sudheer Vemulapalli,C. Fernando,Kenneth J. Maggio,Robert B. Staszewski,N. Barton,Meng-Chang Lee,P. Cruise,Manouchehr Entezari,Khurram Muhammad,Dirk Leipold +14 more
TL;DR: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time.
Journal ArticleDOI
The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process
Khurram Muhammad,Yo-Chuol Ho,T. Mayhugh,Chih-Ming Hung,T. Jung,Imtinan Elahi,Charles Lin,Irene Deng,C. Fernando,John Wallberg,Sudheer Vemulapalli,S. Larson,T. Murphy,Dirk Leipold,P. Cruise,J. Jaehnig,Meng-Chang Lee,Robert Bogdan Staszewski,Roman Staszewski,Ken Maggio +19 more
TL;DR: The receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process is presented.
Patent
Circuit for high-resolution phase detection in a digital RF processor
TL;DR: In this paper, a novel time-to-digital converter (TDC) is used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor.