Suman Datta

TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.

TL;DR: The synthesis of 2D gallium nitride (GaN) via a migration-enhanced encapsulated growth (MEEG) technique utilizing epitaxial graphene is demonstrated and it is established that graphene plays a critical role in stabilizing the direct-bandgap, 2D buckled structure.

TL;DR: In this paper, a gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the SINR, which is a semiconductor device consisting of a top surface and laterally-opposite sidewalls formed on a substrate.

TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.

TL;DR: In this paper, the authors show that surface phonon scattering in the high/spl kappa/ dielectric is the primary cause of channel electron mobility degradation, and demonstrate that metal-gate electrodes, such as the ones with n+ and p+ work functions, are effective in improving channel mobilities to close to those of the conventional SiO/sub 2/poly-Si stack.