Sumantra Seth

Bio: Sumantra Seth is an academic researcher from Texas Instruments. The author has contributed to research in topics: Current mirror & Driver circuit. The author has an hindex of 7, co-authored 26 publications receiving 137 citations.

An integrated linear RF power detector

Abstract: An integrated RF power detector used in wireless communication is presented. The detector uses a unique replica circuitry to compensate for any changes in process or temperature. This results in a high degree of accuracy and a higher dynamic range. The detector has more than 25 dB of dynamic range within +/- 0.5 dB accuracy and is placed in the die along with the power amplifier in a BiCMOS process. The detector runs up to 7 GHz in simulation, though it is tested at 2.4 GHz here. It runs of a 3 V supply and consumes less than 5 mA.

Filter circuit providing low distortion and enhanced flexibility to obtain variable gain amplification

Abstract: A low distortion filter circuit implementing variable gain amplification (VGA). An aspect of the present invention increases the degrees of freedom (number of components which can be independently programmed/changed to corresponding desired values) to achieve a desired combination of D.C. gain and filter characteristics (e.g., corner frequency, Q-factor, notch frequency, etc.). Such additional degrees of freedom are attained by including additional components in either an input block or a feedback block (implemented with reference to an operational amplifier), and by redesigning the other block using principles such as admittance cancellation to remove the effects of such additional components. The blocks are designed such that a terminal of the programmable components is connected to a fixed/constant voltage (e.g., ground). Embodiments implementing bi-quad single amplifier with and without notch are disclosed.

A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process

Abstract: A 2GHz wide input dynamic range (25%–75%) duty cycle corrector (DCC) circuit with ±2% output duty cycle accuracy is presented. This DCC circuit supports input frequency ranging from 1GHz to 2GHz. The proposed circuit is implemented in 45nm low voltage (0.9V to 1.4V) digital CMOS process. Presented DCC consumes only 1.4mW and occupies 0.01 mm2 area. Built-in-self test method is used to test this circuit in production and shows 99.98% pass percentage in silicon.

Slew-rate controlled pad driver in digital cmos process using parasitic device cap

Abstract: A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up transistor is provided, having a source connected to one side of a power supply, having a gate, and having a drain connected to the output node. The PMOS transistor also has a parasitic capacitance between its gate and drain, having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions. A current source generates a current having a level corresponding to the value of the parasitic capacitance, and to provide that current to the gate of the PMOS transistor. A level shifter receives an input signal having a voltage varying in a first range provides as output signal to the gate of the PMOS transistor shifted to a level suitable for the PMOS transistor. An NMOS pull-down transistor is also provided, connected to the other side of the power supply, with a similar and corresponding current source and level shifter as has the PMOS transistor.

Voltage-mode driver with pre-emphasis

Abstract: A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.

A CMOS RF RMS detector for built-in testing of wireless transceivers

Abstract: A CMOS RF RMS detector is introduced. It generates a DC proportional to the RMS voltage amplitude of an RF signal. Its high input impedance and small silicon area make it suitable for the built-in testing (BIT) of critical RF blocks of a transceiver such as a low noise amplifier (LNA) and power amplifier (PA) without affecting their performance and with minimum area overhead. The use of this structure in the fault detection and diagnosis of a wireless transceiver is described and illustrated with an example. The transistor-level implementation of the proposed circuit is discussed in detail. Post-layout simulation results using CMOS 0.35/spl mu/m technology show that this testing device is able to perform an RF to DC conversion at 2.4GHz in a dynamic range of 20dB using an area of only 0.0135mm/sup 2/ and presenting an equivalent input capacitance of 22.5fF.

Systems and methods for providing device-to-device handshaking through a power supply signal

Abstract: Handshaking circuits are provided in a communications cable and in a device operable to be mated with the communications cable. Before a device can utilize the power supply signal of such a communications channel, the two handshaking circuits must sufficiently identify one another over a power supply signal with a decreased voltage. The decreased voltage allows for a cable plug to be provided with a safe, protected power that cannot cause harm to a human. The decreased voltage also reduces the chance that a device can receive a primary power supply signal from the cable before the device sufficiently identifies itself. Accordingly, a laptop may be connected to a portable music player, but the voltage of the power supply signal provided by the laptop to the cable may be decreased on-cable until the handshaking circuit of the portable music player sufficiently performs a handshaking operation with a on-cable handshaking circuit.

A 76- to 81-GHz Multi-Channel Radar Transceiver

Abstract: This paper presents a packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS for both long-range and short-range automotive radars. The chip contains a two-channel transmitter (TX), a six-channel receiver (RX), a local-oscillator (LO) chain, and built-in self-test (BIST) circuitry. Each transmit channel includes multiple variable-gain amplifiers and a two-stage power amplifier. Measured on-die output power per channel is +18 dBm at 25 °C, decreasing to +16 dBm at 125 °C. Each receive channel includes a current-mode mixer, followed by intermediate-frequency buffers. At 25 °C, measured on-die noise figure is 10–11 dB, conversion gain is 14–15 dB, and input 1-dB compression point exceeds +1 dBm. An integrated LO chain drives the transmit and receive chains and includes an 18.5- to 20.6-GHz voltage-controlled oscillator connected to cascaded frequency doublers and a divide-by-four prescaler. At 25 °C, measured phase noise is −100 dBc/Hz at 1-MHz offset from a 77-GHz carrier. Integrated BIST circuits enable the measurement of signal power, RX gain, channel-to-channel phase, and internal temperature. The chip is flip-chip packaged into a ball-grid array and extracted interconnect loss for the package is 1.5 to 2 dB. Total power consumption for the chip is 1.8 W from 3.3 V for a single-TX, six-RX mode.

Low-cost parametric test and diagnosis of RF systems using multi-tone response envelope detection

Abstract: Because of aggressive technology scaling and multi-GHz operating frequencies of radio frequency (RF) devices, parametric failure test and diagnosis of RF circuitry is becoming increasingly important for the reduction of production test cost and faster yield ramp-up. A low-cost test and diagnosis method is proposed for multi-parametric faults in wireless systems that allows for the accurate prediction of the end-to-end specifications as well as the specifications of all the embedded RF modules. The procedure is based on application of an optimised test stimulus and extraction of its transient test response envelopes at RF signal nodes using a simple diode-based envelope detector. The test response is down-converted to lower frequencies compared to the operating frequency, thus eliminating the need to make RF measurements using expensive instrumentation. The specifications as well as the diagnostic information are computed from the test response of the envelope detector using statistical models. It is shown that the resulting information (features) in the transient envelope can accurately predict a host of test specifications using a single test configuration and test response capture event. Hardware measurement data from a 1.575 GHz transceiver shows that the test specifications of the system as well as the modules can be predicted with a high degree of accuracy using this method.

RF front-end system gain and linearity built-in test

Abstract: This work addresses the concurrent on-chip measurement of the gain, the input 1-dB compression point (ICP/sub 1-dB/), and the input-referred third-order interference point (IIP/sub 3/) of individual RF building blocks in RF front-end systems, using introduced high speed CMOS RF on-chip amplitude detectors, which work up to 20 GHz with high accuracy, small area, and low power consumption.