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Sun-Kyu Hwang

Researcher at Samsung

Publications -  19
Citations -  506

Sun-Kyu Hwang is an academic researcher from Samsung. The author has contributed to research in topics: High-electron-mobility transistor & Gate oxide. The author has an hindex of 8, co-authored 19 publications receiving 370 citations.

Papers
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Journal ArticleDOI

Impact of Channel Hot Electrons on Current Collapse in AlGaN/GaN HEMTs

TL;DR: In this paper, the authors studied the current collapse phenomenon during switching in p-GaN gate AlGaN/GaN high-electron-mobility transistors and found that channel hot electrons play a major role in increasing current collapse and that adding a field plate significantly reduces the effect.
Proceedings ArticleDOI

Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic

TL;DR: Wang et al. as discussed by the authors fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies.
Proceedings ArticleDOI

Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic

TL;DR: The manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform is demonstrated by achieving stable functionality and robust package level reliability and read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology.
Proceedings ArticleDOI

1.6kV, 2.9 mΩ cm 2 normally-off p-GaN HEMT device

TL;DR: In this paper, a p-GaN/AlGaN and GaN/GaN based normally-off HEMT device has been demonstrated on a Si substrate and the calculated figure of merit is 921 MV2/Ωcm2, which is the highest value reported for the GaN E-mode devices.
Proceedings ArticleDOI

1Gbit High Density Embedded STT-MRAM in 28nm FDSOI Technology

TL;DR: In this paper, a high density 1Gb embedded STT-MRAM in 28nm FDSOI technology was successfully demonstrated, which was mainly attributed to the advanced process for better control of MTJ CD, highly manufacturable process window and robust circuit design for high density chip.