Sunetra K. Mendis

Bio: Sunetra K. Mendis is an academic researcher from California Institute of Technology. The author has contributed to research in topics: CMOS & Image sensor. The author has an hindex of 12, co-authored 14 publications receiving 2294 citations. Previous affiliations of Sunetra K. Mendis include Jet Propulsion Laboratory & Columbia University.

Active pixel sensor with intra-pixel charge transfer

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

CMOS active pixel image sensors for highly integrated imaging systems

Abstract: A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-/spl mu/m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 /spl mu/m/spl times/40 /spl mu/m with 26% fill-factor. Array sizes of 28/spl times/28 elements and 128/spl times/128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 /spl mu/V/e/sup -/ for the p-well devices and 6.5 /spl mu/V/e/sup -/ for the n-well devices. Input referred read noise of 28 e/sup -/ rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed.

CMOS active pixel image sensor

Abstract: A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 /spl mu/m double-poly, double-metal foundry CMOS process and is realized as a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications. >

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

A 128/spl times/128 CMOS active pixel image sensor for highly integrated imaging systems

Abstract: A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 /spl mu/m p-well CMOS process, and consists of a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community. >

Imaging system for vehicle

Abstract: An imaging system for a vehicle includes an imaging device having a field of view exteriorly and forward of the vehicle in its direction of travel, and an image processor operable to process the captured images in accordance with an algorithm. The algorithm comprises a sign recognition routine and a character recognition routine. The image processor processes the image data captured by the imaging device to detect signs in the field of view of the imaging device and applies the sign recognition routine to determine a sign type of the detected sign. The image processor is operable to apply the character recognition routine to the image data to determine information on the detected sign. The image processor applies the character recognition routine to the captured images in response to an output of the sign recognition routine being indicative of the detected sign being a sign type of interest.

CMOS image sensors: electronic camera-on-a-chip

Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

Methods and apparatus for measuring analytes using large scale fet arrays

Abstract: An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Vehicle headlight control using imaging sensor

Abstract: A vehicle headlamp control method and apparatus includes providing an imaging sensor that senses light in spatially separated regions of a field of view forward of the vehicle. Light levels sensed in individual regions of the field of view are evaluated in order to identify light sources of interest, such as oncoming headlights and leading taillights. The vehicle's headlights are controlled in response to identifying such particular light sources or absence of such light sources. Spectral signatures of light sources may be examined in order to determine if the spectral signature matches that of particular light sources such as the spectral signatures of headlights or taillights. Sensed light levels may also be evaluated for their spatial distribution in order to identify light sources of interest.

Active pixel sensor with intra-pixel charge transfer

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.