Sunhae Shin

Bio: Sunhae Shin is an academic researcher from Ulsan National Institute of Science and Technology. The author has contributed to research in topics: CMOS & Inverter. The author has an hindex of 7, co-authored 20 publications receiving 150 citations.

Tunnelling-based ternary metal–oxide–semiconductor technology

Abstract: The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. Quantum-mechanical band-to-band tunnelling can be used to create an energy-efficient ternary logic technology that can be fabricated on the wafer scale using complementary metal–oxide–semiconductor (CMOS) processes.

Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology

Abstract: We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMOS inverter by TCAD device and mixed-mode circuit simulation with 32-nm high- $\kappa $ /metal-gate technology. Through analytical device modeling on BTBT and subthreshold current, static noise margin (SNM), off-leakage variation (OLV), and operation voltage ( $V_{\mathrm {DD}})$ scaling limits of STI have been investigated. The typical SNM is 200 mV and the variability of the intermediate level ( $\Delta V_{\mathrm {OM}}\sim 50$ mV) from OLV can be allowable into the worst SNM (>100 mV) of STI operation at $V_{\mathrm {DD}}= 1$ V. Exponentially reduced BTBT off-leakage around minimum $V_{\mathrm {DD}}\sim 0.1$ V is promising for ultimate low-power application of our STI.

A Novel Ternary Multiplier Based on Ternary CMOS Compact Model

Abstract: Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design, we construct a standardternary-cell library and exploit a ternary static timing analysis(T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.

Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

Abstract: In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

Ultra-low standby power and static noise-immune standard ternary inverter based on nanoscale ternary CMOS technology

Abstract: We demonstrate ternary CMOS (Γ-CMOS)-based standard ternary inverter (STI) for compact and power-scalable multi-valued logic (MVL) circuits. The distinguished mechanism of F G -independent junction band-to-band tunneling (BTBT) for ternary logic has been successfully obtained by CMOS process with a few pA/μm level which enables STI operation with ultra-low static power consumption of 7.7 pW/μm. Through the STI performance investigation with various Γ-CMOS structures by using TCAD simulation, advanced nanoscale bulk tri-gate (TG) ternary FinFET (T-FinFET) shows highly noise-immune STI operation with a larger static noise margin (SNM) of 94% to the ideal SNM (230mV) than 86% of bulk planar T-CMOS and 75% of SOI T-CMOS technology.

Cu 2 ZnSnS 4 solar cells with over 10% power conversion efficiency enabled by heterojunction heat treatment

Abstract: Sulfide kesterite Cu2ZnSnS4 provides an attractive low-cost, environmentally benign and stable photovoltaic material, yet the record power conversion efficiency for such solar cells has been stagnant at around 9% for years. Severe non-radiative recombination within the heterojunction region is a major cause limiting voltage output and overall performance. Here we report a certified 11% efficiency Cu2ZnSnS4 solar cell with a high 730 mV open-circuit voltage using heat treatment to reduce heterojunction recombination. This heat treatment facilitates elemental inter-diffusion, directly inducing Cd atoms to occupy Zn or Cu lattice sites, and promotes Na accumulation accompanied by local Cu deficiency within the heterojunction region. Consequently, new phases are formed near the hetero-interface and more favourable conduction band alignment is obtained, contributing to reduced non-radiative recombination. Using this approach, we also demonstrate a certified centimetre-scale (1.11 cm2) 10% efficiency Cu2ZnSnS4 photovoltaic device; the first kesterite cell (including selenium-containing) of standard centimetre-size to exceed 10%. The emerging kesterite Cu2ZnSnS4 solar cell offers a potential low-cost, non-toxic, materially abundant platform for next-generation photovoltaics, yet its efficiency has been mired below 10%. Yan et al. now use post-heat treatment of the heterojunction to show device efficiencies that surpass 10%.

Silicon Vlsi Technology Fundamentals Practice And Modeling

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2D materials-based homogeneous transistor-memory architecture for neuromorphic hardware.

Abstract: In neuromorphic hardware, peripheral circuits and memories based on heterogeneous devices are generally physically separated. Thus, exploration of homogeneous devices for these components is key fo...

A high-conductivity n-type polymeric ink for printed electronics.

Abstract: Conducting polymers, such as the p-doped poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), have enabled the development of an array of opto- and bio-electronics devices. However, to make these technologies truly pervasive, stable and easily processable, n-doped conducting polymers are also needed. Despite major efforts, no n-type equivalents to the benchmark PEDOT:PSS exist to date. Here, we report on the development of poly(benzimidazobenzophenanthroline):poly(ethyleneimine) (BBL:PEI) as an ethanol-based n-type conductive ink. BBL:PEI thin films yield an n-type electrical conductivity reaching 8 S cm−1, along with excellent thermal, ambient, and solvent stability. This printable n-type mixed ion-electron conductor has several technological implications for realizing high-performance organic electronic devices, as demonstrated for organic thermoelectric generators with record high power output and n-type organic electrochemical transistors with a unique depletion mode of operation. BBL:PEI inks hold promise for the development of next-generation bioelectronics and wearable devices, in particular targeting novel functionality, efficiency, and power performance. The development of n-type conductive polymer inks is critical for the development of next-generation opto-electronic devices that rely on efficient hole and electron transport. Here, the authors report an alcohol-based, high performance and stable n-type conductive ink for printed electronics.