Given the increasing impact of Rowhammer, and the dearth of adequate other hardware defenses, many in the security community have pinned their hopes on error-correcting code (ECC) memory as one of the few practical defenses against Rowhammer attacks. Specifically, the expectation is that the ECC algorithm will correct or detect any bits they manage to flip in memory in real-world settings. However, the extent to which ECC really protects against Rowhammer is an open research question, due to two key challenges. First, the details of the ECC implementations in commodity systems are not known. Second, existing Rowhammer exploitation techniques cannot yield reliable attacks in presence of ECC memory. In this paper, we address both challenges and provide concrete evidence of the susceptibility of ECC memory to Rowhammer attacks. To address the first challenge, we describe a novel approach that combines a custom-made hardware probe, Rowhammer bit flips, and a cold boot attack to reverse engineer ECC functions on commodity AMD and Intel processors. To address the second challenge, we present ECCploit, a new Rowhammer attack based on composable, data-controlled bit flips and a novel side channel in the ECC memory controller. We show that, while ECC memory does reduce the attack surface for Rowhammer, ECCploit still allows an attacker to mount reliable Rowhammer attacks against vulnerable ECC memory on a variety of systems and configurations. In addition, we show that, despite the non-trivial constraints imposed by ECC, ECCploit can still be powerful in practice and mimic the behavior of prior Rowhammer exploits.

https://www.computer.org/csdl/pds/api/csdl/proceedings/download-article/19skfwyNp5e/pdf

Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks

Modern computing systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in computing that cause performance, scalability and energy bottlenecks: (1) data access is a key bottleneck as many important applications are increasingly data-intensive, and memory bandwidth and energy do not scale well, (2) energy consumption is a key limiter in almost all computing platforms, especially server and mobile systems, (3) data movement, especially off-chip to on-chip, is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many technology scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of higher cost. The emergence of 3D-stacked memory plus logic, the adoption of error correcting codes inside the latest DRAM chips, proliferation of different main memory standards and chips, specialized for different purposes (e.g., graphics, low-power, high bandwidth, low latency), and the necessity of designing new solutions to serious reliability and security issues, such as the RowHammer phenomenon, are an evidence of this trend. This chapter discusses recent research that aims to practically enable computation close to data, an approach we call processing-in-memory (PIM). PIM places computation mechanisms in or near where the data is stored (i.e., inside the memory chips, in the logic layer of 3D-stacked memory, or in the memory controllers), so that data movement between the computation units and memory is reduced or eliminated.

A Modern Primer on Processing in Memory.

Experimental characterization of DRAM errors is a powerful technique for understanding DRAM behavior and provides valuable insights for improving overall system performance, energy efficiency, and reliability. Unfortunately, recent DRAM technology scaling issues are forcing manufacturers to adopt on-die error-correction codes (ECC), which pose a significant challenge for DRAM error characterization studies by obfuscating raw error distributions using undocumented, proprietary, and opaque error-correction hardware. As we show in this work, errors observed in devices with on-die ECC no longer follow expected, well-studied distributions (e.g., lognormal retention times) but rather depend on the particular ECC scheme used.

Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices

In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408x DDR3, 652x DDR4, and 520x LPDDR4) from 300 DRAM modules (60x DDR3, 110x DDR4, and 130x LPDDR4) with RowHammer protection mechanisms disabled, spanning multiple different technology nodes from across each of the three major DRAM manufacturers. Our studies definitively show that newer DRAM chips are more vulnerable to RowHammer: as device feature size reduces, the number of activations needed to induce a RowHammer bit flip also reduces, to as few as 9.6k (4.8k to two rows each) in the most vulnerable chip we tested. 
We evaluate five state-of-the-art RowHammer mitigation mechanisms using cycle-accurate simulation in the context of real data taken from our chips to study how the mitigation mechanisms scale with chip vulnerability. We find that existing mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future devices given our observed trends of RowHammer vulnerability. Thus, it is critical to research more effective solutions to RowHammer.

Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

A Review on Power Supply Induced Jitter

An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of the victim buffer with power-supply voltage fluctuations were calculated and validated by comparisons with HSPICE and experimental results. The obtained PDFs due to power-supply voltage fluctuations could be combined with the statistical link simulation methods for quick estimation of bit error rate (BER).

Analytical Probability Density Calculation for Step Pulse Response of a Single-Ended Buffer With Arbitrary Power-Supply Voltage Fluctuations

The internet of things (IoT) requires that more data are collected and processed by devices with faster response, but lower power consumption. In order to achieve these unprecedented requirements, a high-speed DRAM with low-power dissipation at standby and during low-frequency operation in a small footprint is necessary. In addition, a higher degree of reliability is expected for some applications: such as transportation and healthcare. One promising solution, on-chip error correction coding (ECC), has gained traction among memory companies [1] and is now required by the LPDDR4 standard for the first time [2]. In this paper, a 2Gb LPDDR4 that dissipates 75% less refresh current than a conventional LPDDR4 is presented. The proposed LPDDR4 exploits ECC to reduce refresh current, periodically activated voltage regulators to reduce standby power, and dual CA buffers to save the buffer current during low frequency operation. In addition, circuit designs for cell screen of DRAM with on-chip ECC, and for high-speed wafer test for known good die (KGD) - essential for small form factor devices using system-in-package (SiP) - are presented.

23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications

Statistical BER Analysis due to Supply Voltage Fluctuations at a Single-Ended Buffer

In this paper, we will compare the use of various optical inspection technologies to find critical defects in IC substrates during the manufacturing process with the goal of improving yield. We will also introduce a unique inspection technology for the detection of critical defects which are difficult to identify using traditional technologies.

Sunki Cho

Papers

Analytical Probability Density Calculation for Step Pulse Response of a Single-Ended Buffer With Arbitrary Power-Supply Voltage Fluctuations

23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications

Statistical BER Analysis due to Supply Voltage Fluctuations at a Single-Ended Buffer

Inspection Solutions for Advanced IC Substrate Process Control