A compact model for multi-gate MOSFETs with two independently-biased gates is presented. The core model is verified against TCAD simulations without the use of any fitting parameters. Real device effects such as short channel effects and body doping effects are captured. The use of the model is demonstrated through two simulation examples: (1) Back-gate dynamic feedback of FinFET SRAM cells and (2) Tuning of device variations through back gate biasing.

AMulti-Gate MOSFET CompactModelFeaturing Independent-Gate Operation

Advances in technology leads to dramatic lowering of MOSFET channel length. However short channel effects (SCE) degrade device performance and put a limit to scaling down of device dimensions. Drain Induced Barrier Lowering (DIBL) is such an effect where threshold voltage rolls off and sub-threshold current increases significantly. Study of the surface potential is important for understanding DIBL. In this paper we propose a numerical model to calculate the variation in surface potential by solving the 2-D Poisson's equation, starting from a more accurate expression for the charge distribution. The results agree with the expected trend.

Estimation of surface potential variation in short channel MOSFET by solving 2D Poisson's equation

Research on double-gate MOSFET has already exhibited several novel solutions of existing problems like reducing leakage current or short-channel effect. For both long-channel structure or microscopic devices, the role of the bottom-gate becomes more critical for making higher ON-to-OFF current ratio, and therefore, individual-gate architecture becomes more popular than tied-gate architecture owing to the possibility of individual tuning. Junctionless devices come into the limelight due to better mobility control than the other DG configurations, and considered the subject of investigation in the last few years. The current chapter investigates the effect of negative bottom gate voltage on the analog and RF performances of Asymmetric Junctionless Dual Material Double Gate (AJDMDG) MOSFET. TCAD device simulator was used to investigate the effect of negative bottom gate voltage on analog and RF parameters. The results show that utilizing a low value of the work function of the bottom gate terminal improved the analog and RF performance. 

Impact of Negative Bottom Gate Voltage for Improvement of RF/Analog Performance in Asymmetric Junctionless Dual Material Double Gate MOSFET

Surface potential of symmetric double gate MOSFET is analytically investigated by solving Poisson's equation subject to appropriate boundary conditions considering the presence of both free and doped carriers. Different semiconductors are considered for simulation purpose to find the change in potential w.r.t to the already existing results for Si, and carrier concentrations are modified within feasible limit to observe the variation. Simulations are also carried out at different temperatures in order to account the Joule heat effect at on-chip, and significant variations are observed. Result will play key role in determining drain current through DG MOSFET which satisfies Ortiz-Conde model.

Supoma Bhowmick

Papers

Computing Surface Potential of Double Gate MOSFET for both Free and Doped Carrier Concentrations