Surendra Hemaram

Bio: Surendra Hemaram is an academic researcher from Indian Institute of Technology, Jodhpur. The author has contributed to research in topics: Monte Carlo method & Capacitor. The author has co-authored 4 publications. Previous affiliations of Surendra Hemaram include Indian Institutes of Technology.

Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm

Abstract: This paper discusses a discrete optimization problem of optimal design of Power Delivery Networks (PDN) in VLSI systems. In this paper, a practical case study is presented, where, in order to design an efficient PDN, the cumulative impedance of the PDN is optimized below the target impedance. For this purpose, the decoupling capacitors (from commercially available capacitors) are chosen in such a way that the minimum number of the capacitors are used, and also their optimal locations are identified. The different variants of inertia weight strategies incorporated into particle swarm optimization algorithms are used for this purpose. A comparative analysis of the performance of these algorithms is also presented.

Metaheuristic Optimization of Decoupling Capacitors in a Power Delivery Network

Abstract: In VLSI circuits and systems, it is a common practice to reduce power supply noise in power delivery networks by decoupling capacitors. The optimal selection and placement of decoupling capacitors is crucial for maintaining power integrity efficiently. This paper presents a metaheuristic technique based generic framework for decoupling capacitor optimization in a practical power delivery network. The cumulative impedance of a power delivery network is minimized below the target impedance by optimal selection and placement of decoupling capacitors using state-of-the-art metaheuristic algorithms. A comparative analysis of the performance of these algorithms is presented with the insights of practical implementation.

An Automated Framework for Variability Analysis using Simulated Annealing

Abstract: In the design process of integrated circuits, design and process variability plays an important role in the performance of the circuits. In this paper, an automated framework for Variability Analysis of CMOS circuits is proposed using simulated annealing algorithm. A practical study of variability analysis of phase noise in a 2.4 GHz CMOS oscillator is illustrated using this framework. The performance for the proposed framework for Variability Analysis application is validated by comparing it with the conventional Monte Carlo simulations. A significant gain in terms of computational time is reported.

A Swarm Intelligence based Automated Framework for Variability Analysis

Abstract: In this paper, a novel methodology for variability analysis of CMOS circuits is presented. An automated framework is proposed that uses swarm intelligence based optimization technique, namely particle swarm optimization algorithm, to estimate the worst-case variability bounds of the system response. The efficacy of the proposed method is illustrated by performing the variability in phase noise of a 2.4 GHz CMOS LC tank RF oscillator. The proposed methodology is investigated and validated by comparing it with the conventional Monte Carlo simulations technique. For this case study, the proposed method is found to be significantly time-efficient.

Computational Intelligence Based Selection and Placement of Decoupling Capacitors: A Comparative Study

Abstract: In high-speed VLSI systems, decoupling capacitors are the key components to minimize power supply noise in power delivery networks. For efficiently maintaining power integrity in these systems, optimal selection and placement of decoupling capacitors is necessary. This paper presents a computational intelligence based generic framework to solve the industrial problem of decoupling capacitor optimization in a practical power delivery network using metaheuristic algorithms. The cumulative impedance of a power delivery network is minimized below the target impedance by optimal selection and placement of decoupling capacitors using the state-of-the-art metaheuristic algorithms. A comparative analysis of the performance of these algorithms is presented with the insights of practical implementation.

Bridging the Gap between Physical and Circuit Analysis for Variability-Aware Microwave Design: Modeling Approaches

Abstract: Process-induced variability is a growing concern in the design of analog circuits, and in particular for monolithic microwave integrated circuits (MMICs) targeting the 5G and 6G communication systems. The RF and microwave (MW) technologies developed for the deployment of these communication systems exploit devices whose dimension is now well below 100 nm, featuring an increasing variability due to the fabrication process tolerances and the inherent statistical behavior of matter at the nanoscale. In this scenario, variability analysis must be incorporated into circuit design and optimization, with ad hoc models retaining a direct link to the fabrication process and addressing typical MMIC nonlinear applications like power amplification and frequency mixing. This paper presents a flexible procedure to extract black-box models from accurate physics-based simulations, namely TCAD analysis of the active devices and EM simulations for the passive structures, incorporating the dependence on the most relevant fabrication process parameters. We discuss several approaches to extract these models and compare them to highlight their features, both in terms of accuracy and of ease of extraction. We detail how these models can be implemented into EDA tools typically used for RF and MMIC design, allowing for fast and accurate statistical and yield analysis. We demonstrate the proposed approaches extracting the black-box models for the building blocks of a power amplifier in a GaAs technology for X-band applications.

An Automated Framework for Variability Analysis for Integrated Circuits Using Metaheuristics

Abstract: This work aims to analyze the variability of integrated circuits and systems. An automated framework is presented for variability analysis that exploits the metaheuristic optimization techniques. The efficacy of the proposed approach is demonstrated by two case studies—one is the estimation of variability in phase noise in RF CMOS LC tank oscillators (frequency domain analysis) and the other is the estimation of variability in the differential output signal of a current mode driver (time-domain analysis). The proposed approach is investigated and validated by comparing the results from the traditional Monte Carlo simulations and the ordinary least-squares-based polynomial chaos expansion. A significant gain in the computational time is reported while maintaining accuracy in the results. The proposed methodology is not just limited to variability analysis applications but also can be used to solve the circuit optimization problems.

An Automated Framework for Variability Analysis for Integrated Circuits Using Metaheuristics

Abstract: This work aims to analyze the variability of integrated circuits and systems. An automated framework is presented for variability analysis that exploits the metaheuristic optimization techniques. The efficacy of the proposed approach is demonstrated by two case studies- one is the estimation of variability in phase noise in RF CMOS LC tank oscillators (frequency domain analysis) and other being the estimation of variability in the differential output signal of a current mode driver (time-domain analysis). The proposed approach is investigated and validated by comparing the results from the traditional Monte-Carlo simulations and the Ordinary-Least Squares based Polynomial Chaos Expansion. A significant gain in the computational time is reported while maintaining accuracy in the results. The proposed methodology is not just limited to variability analysis applications but also can be used to solve the circuit optimization problems.

MCB-DPO: Multiport Constrained Barrier Method-Based Decoupling Capacitor Placement Optimization on Irregularly Shaped Planes

Abstract: A multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs). The proposed method is based on barrier methods and can simultaneously handle multiple ball grid array (BGA) devices and capacitor ports on practical power/ground plane pairs of polygonal shapes without restriction in the problem geometry. Semi-analytical expressions are developed for the magnitude of device port impedance that is set as the objective function. The placement optimization problem including constraints of planar boundaries and impedance specifications is cast into a matrix expression that meets Karush–Kuhn Tucker (KKT) conditions and solved through Newton–Raphson (N–R) iterations. The convergence of iterations is ensured by guaranteeing the positive definiteness of the system matrix through the Levenberg–Marquardt algorithm. Mutual coupling among multiple ports and discrete components of the problem domain is accounted for via matrix calculus techniques applied to the partial derivatives of optimization variables. The derivatives are evaluated accurately exploiting the semi-analytical relations developed for the distributed planar impedance. The proposed method is tested with several examples, and the results are observed to be in good agreement with those obtained from a numerical electromagnetic (EM) simulator while yielding significant speed-up.

Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination

Abstract: Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.