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Sushma R. Huddar

Bio: Sushma R. Huddar is an academic researcher. The author has contributed to research in topics: Field-programmable gate array & Arithmetic logic unit. The author has an hindex of 5, co-authored 5 publications receiving 160 citations.

Papers
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Proceedings ArticleDOI
22 Mar 2013
TL;DR: A novel architecture to perform high speed multiplication using ancient Vedic maths techniques and a new high speed approach utilizing 4:2 compressors and novel 7:1 compressors for addition has been incorporated in the same and has been explored.
Abstract: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.

76 citations

Proceedings ArticleDOI
26 Jul 2012
TL;DR: This paper proposes a novel and unique algorithm to segregate and detect pests using image processing and aims at pest detection not only in a greenhouse environment but also in a farm environment as well.
Abstract: Enormous agricultural yield is lost every year, due to rapid infestation by pests and insects. A lot of research is being carried out worldwide to identify scientific methodologies for early detection/identification of these bio-aggressors. In the recent past, several approaches based on automation and image processing have come to light to address this issue. Most of the algorithms concentrate on pest identification and detection, limited to a greenhouse environment. Also, they involve several complex calculations to achieve the same. In this paper, we propose a novel and unique algorithm to segregate and detect pests using image processing. The proposed methodology involves reduced computational complexity and aims at pest detection not only in a greenhouse environment but also in a farm environment as well. The whitefly, a bio-aggressor which poses a threat to a multitude of crops, was chosen as the pest of interest in this paper. The algorithm was tested for several whiteflies affecting different leaves and an accuracy of 96% of whitefly detection was achieved. The algorithm was developed and implemented using MATLAB programming language on MATLAB 7.1 build 2011a.

51 citations

Proceedings ArticleDOI
19 Jun 2014
TL;DR: An automated thresholding algorithm for segmentation of the Braille dots along with a novel algorithm for identification of the characters has been explained and found to be four times faster than many existing methodologies, on the FPGA.
Abstract: With the introduction and popularization of text to speech convertors, a huge drop in literacy rates is being seen amongst the visually impaired. Also, since Braille is not well known to the masses, communication by the visually impaired with the outside world becomes an arduous task. A lot of research is being carried out in conversion of English text to Braille but not many concentrate on the alternative i.e. conversion of Braille to regional languages. In order to address this issue, in this paper we introduce a novel methodology to convert Braille characters representing the Kannada Language (a popular language of southern part of India), captured by a camera, into Kannada text or speech. An automated thresholding algorithm for segmentation of the Braille dots along with a novel algorithm for identification of the characters has been explained. All algorithms were designed and developed for a Xilinx Spartan 3E FPGA and were executed in real time. An accuracy of over 94% was achieved in Braille segmentation and detection. The algorithm for identification of the Kannada Braille character was found to be four times faster than many existing methodologies, on the FPGA.

19 citations

Proceedings ArticleDOI
21 Oct 2013
TL;DR: A novel and area efficient architecture for performing the mix columns & inverse mix columns operation, which is the major operation in the Advanced Encryption Standard (AES) method of cryptography is proposed using ancient Vedic Mathematics techniques.
Abstract: With the ever increasing demand for secure transactions in banking and also in mail delivery systems, encryption and decryption using cryptography plays a very important role. Nowadays, with 90% of secure transactions occurring on smart phones and other hand-held devices, a low on-chip area and a high speed algorithm to perform the same becomes the need for the day. In order to meet this requirement, several algorithms have been designed and implemented in the past, but each of these algorithms possess their own shortcomings with respect to an ASIC or an FPGA implementation. In this paper, we propose a novel and area efficient architecture for performing the mix columns & inverse mix columns operation, which is the major operation in the Advanced Encryption Standard (AES) method of cryptography. We perform the same using ancient Vedic Mathematics techniques. The cryptographic unit involving mix columns & inverse mix columns for AES was designed and implemented on a Xilinx Spartan 3e series of FPGA. A 100% area efficiency and a 2 times increase in speed was achieved by the novel algorithm, in comparison with two other popular implementations of the same.

15 citations

Book ChapterDOI
18 Jan 2013
TL;DR: A novel, area efficient and high speed architecture to implement a Vedic mathematics multiplier based on Urdhva Tiryakbhyam methodology is proposed and its performance was compared with the existing ALU designs.
Abstract: High speed and area efficient multiplier architecture plays a vital role in Arithmetic Logic Unit (ALU) design, especially when it comes to low power implementation of Central Processing Units, Microprocessors and Microcontrollers. In this paper, we propose a novel, area efficient and high speed architecture to implement a Vedic mathematics multiplier based on Urdhva Tiryakbhyam methodology. The same was utilized within an ALU and its performance was compared with the existing ALU designs. It was found that the proposed methodology is around 2 times faster than the existing ALU architectures. Also a significant 3% decrease in area, in comparison with existing designs was obtained. The proposed algorithm was designed and implemented using Verilog RTL on a Xilinx Spartan 3e FPGA and compared with other algorithms. The results prove that the proposed architecture could be a great boon for high speed and low area based processor design.

12 citations


Cited by
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Journal Article
TL;DR: Der DES basiert auf einer von Horst Feistel bei IBM entwickelten Blockchiffre („Lucipher“) with einer Schlüssellänge von 128 bit zum Sicherheitsrisiko, und zuletzt konnte 1998 mit einem von der „Electronic Frontier Foundation“ (EFF) entwickkelten Spezialmaschine mit 1.800 parallel arbeit
Abstract: Im Jahre 1977 wurde der „Data Encryption Algorithm“ (DEA) vom „National Bureau of Standards“ (NBS, später „National Institute of Standards and Technology“ – NIST) zum amerikanischen Verschlüsselungsstandard für Bundesbehörden erklärt [NBS_77]. 1981 folgte die Verabschiedung der DEA-Spezifikation als ANSI-Standard „DES“ [ANSI_81]. Die Empfehlung des DES als StandardVerschlüsselungsverfahren wurde auf fünf Jahre befristet und 1983, 1988 und 1993 um jeweils weitere fünf Jahre verlängert. Derzeit liegt eine Neufassung des NISTStandards vor [NIST_99], in dem der DES für weitere fünf Jahre übergangsweise zugelassen sein soll, aber die Verwendung von Triple-DES empfohlen wird: eine dreifache Anwendung des DES mit drei verschiedenen Schlüsseln (effektive Schlüssellänge: 168 bit) [NIST_99]. Der DES basiert auf einer von Horst Feistel bei IBM entwickelten Blockchiffre („Lucipher“) mit einer Schlüssellänge von 128 bit. Da die amerikanische „National Security Agency“ (NSA) dafür gesorgt hatte, daß der DES eine Schlüssellänge von lediglich 64 bit besitzt, von denen nur 56 bit relevant sind, und spezielle Substitutionsboxen (den „kryptographischen Kern“ des Verfahrens) erhielt, deren Konstruktionskriterien von der NSA nicht veröffentlicht wurden, war das Verfahren von Beginn an umstritten. Kritiker nahmen an, daß es eine geheime „Trapdoor“ in dem Verfahren gäbe, die der NSA eine OnlineEntschlüsselung auch ohne Kenntnis des Schlüssels erlauben würde. Zwar ließ sich dieser Verdacht nicht erhärten, aber sowohl die Zunahme von Rechenleistung als auch die Parallelisierung von Suchalgorithmen machen heute eine Schlüssellänge von 56 bit zum Sicherheitsrisiko. Zuletzt konnte 1998 mit einer von der „Electronic Frontier Foundation“ (EFF) entwickelten Spezialmaschine mit 1.800 parallel arbeitenden, eigens entwickelten Krypto-Prozessoren ein DES-Schlüssel in einer Rekordzeit von 2,5 Tagen gefunden werden. Um einen Nachfolger für den DES zu finden, kündigte das NIST am 2. Januar 1997 die Suche nach einem „Advanced Encryption Standard“ (AES) an. Ziel dieser Initiative ist, in enger Kooperation mit Forschung und Industrie ein symmetrisches Verschlüsselungsverfahren zu finden, das geeignet ist, bis weit ins 21. Jahrhundert hinein amerikanische Behördendaten wirkungsvoll zu verschlüsseln. Dazu wurde am 12. September 1997 ein offizieller „Call for Algorithm“ ausgeschrieben. An die vorzuschlagenden symmetrischen Verschlüsselungsalgorithmen wurden die folgenden Anforderungen gestellt: nicht-klassifiziert und veröffentlicht, weltweit lizenzfrei verfügbar, effizient implementierbar in Hardund Software, Blockchiffren mit einer Blocklänge von 128 bit sowie Schlüssellängen von 128, 192 und 256 bit unterstützt. Auf der ersten „AES Candidate Conference“ (AES1) veröffentlichte das NIST am 20. August 1998 eine Liste von 15 vorgeschlagenen Algorithmen und forderte die Fachöffentlichkeit zu deren Analyse auf. Die Ergebnisse wurden auf der zweiten „AES Candidate Conference“ (22.-23. März 1999 in Rom, AES2) vorgestellt und unter internationalen Kryptologen diskutiert. Die Kommentierungsphase endete am 15. April 1999. Auf der Basis der eingegangenen Kommentare und Analysen wählte das NIST fünf Kandidaten aus, die es am 9. August 1999 öffentlich bekanntmachte: MARS (IBM) RC6 (RSA Lab.) Rijndael (Daemen, Rijmen) Serpent (Anderson, Biham, Knudsen) Twofish (Schneier, Kelsey, Whiting, Wagner, Hall, Ferguson).

624 citations

Journal ArticleDOI
TL;DR: An automatic and effective tomato fruit grading system based on computer vision techniques is proposed and it was observed that the proposed method was successful with 96.47% accuracy in evaluating the quality of the tomato.

121 citations

Journal ArticleDOI
TL;DR: The aim of the present paper is to review the techniques and scientific state of the art of the use of sensors for automatic detection and monitoring of insect pests, presenting the different systems available, examples of applications and recent developments, including machine learning and Internet of Things.
Abstract: Many species of insect pests can be detected and monitored automatically. Several systems have been designed in order to improve integrated pest management (IPM) in the context of precision agriculture. Automatic detection traps have been developed for many important pests. These techniques and new technologies are very promising for the early detection and monitoring of aggressive and quarantine pests. The aim of the present paper is to review the techniques and scientific state of the art of the use of sensors for automatic detection and monitoring of insect pests. The paper focuses on the methods for identification of pests based in infrared sensors, audio sensors and image-based classification, presenting the different systems available, examples of applications and recent developments, including machine learning and Internet of Things. Future trends of automatic traps and decision support systems are also discussed.

108 citations

Journal ArticleDOI
TL;DR: A novel approach for the detection and monitoring of adult-stage whitefly and thrip in greenhouses based on the combination of an image-processing algorithm and artificial neural networks is proposed.

76 citations

Journal ArticleDOI
TL;DR: A new system, based on digital image processing, to quantify whiteflies on soybean leaves, that allows counting to be fully automated, considerably speeding up the process in comparison with the manual approach.
Abstract: This paper presents a new system, based on digital image processing, to quantify whiteflies on soybean leaves. This approach allows counting to be fully automated, considerably speeding up the process in comparison with the manual approach. The proposed algorithm is capable of detecting and quantifying not only adult whiteflies, but also specimens in the nymph stage. A complete performance evaluation is presented, with emphasis on the conditions and situations for which the algorithm succeeds, and also on the circumstances that need further work. Although this proposal was entirely developed using soybean leaves, it can be easily extended to other kinds of crops with little or no changes in the algorithm. The system employs only widely used image processing operations, so it can be easily implemented in any image processing software package.

61 citations