S
Suzuki Makoto
Researcher at Hitachi
Publications - 90
Citations - 1238
Suzuki Makoto is an academic researcher from Hitachi. The author has contributed to research in topics: CMOS & Semiconductor. The author has an hindex of 17, co-authored 90 publications receiving 1223 citations.
Papers
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Journal ArticleDOI
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
Suzuki Makoto,Norio Ohkubo,T. Shinbo,Toshiaki Yamanaka,Akihiro Shimizu,Katsuro Sasaki,Y. Nakagome +6 more
TL;DR: A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path and the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU.
Journal ArticleDOI
A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer
Norio Ohkubo,Suzuki Makoto,T. Shinbo,Toshiaki Yamanaka,Akihiro Shimizu,K. Sasaki,Y. Nakagome +6 more
TL;DR: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology and a new 4-2 compressor and a carry lookahead adder (CLA) have been developed to enhance the speed performance.
Journal ArticleDOI
Ultra-high-speed multiple-quantum-well electro-absorption optical modulators with integrated waveguides
TL;DR: In this paper, the input and output waveguides were integrated with a multiple-quantum-well (MQW) electro-absorption (EA) optical modulator to achieve ultra-high-speed modulation while keeping the total device length long enough for easy fabrication and packaging.
Patent
Semiconductor optical device and method for fabricating the same
TL;DR: In this article, a semiconductor optical device is fabricated on a single substrate using a plurality of stripe type insulating thin film masks, which are formed over a region of the semiconductor substrate which has optical waveguides formed therein.
Patent
Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
TL;DR: In this paper, a multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks.