scispace - formally typeset
Search or ask a question
Author

Sven Lütkemeier

Other affiliations: Bielefeld University
Bio: Sven Lütkemeier is an academic researcher from University of Paderborn. The author has contributed to research in topics: CMOS & Subthreshold conduction. The author has an hindex of 5, co-authored 8 publications receiving 283 citations. Previous affiliations of Sven Lütkemeier include Bielefeld University.

Papers
More filters
Journal ArticleDOI
TL;DR: A novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels and does not require a static current flow and can therefore offer considerable static power savings is proposed.
Abstract: In this brief, we propose a novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. The circuit has been optimized and simulated in a 90-nm process technology. It operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage side. At the target design voltage of 200 mV, the level shifter has a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. For a 1-MHz input signal, the total energy per transition is 93.9 fJ. Simulation results are compared to an existing subthreshold to above-threshold level shifter implementation from the paper of Chen et al.

163 citations

Journal ArticleDOI
TL;DR: An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage SRAM based on a flexible and extensible architecture that provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation is fabricated.
Abstract: An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

87 citations

01 Jan 2010
TL;DR: This paper shows that the support of MOP algorithms is necessary and beneficial in the design process of sub-threshold CMOS logic standard cells and results are presented for an inverter, NAND gate, and NOR gate in a 65 nm process technology.
Abstract: Transistor sizing of sub-threshold standard cells for digital ultra-low power systems is a very challenging task because robustness has to be considered as an important design objective in addition to the competing resources power consumption and propagation delay. In this paper we regard this task as a multiobjective optimization problem (MOP) and show that the support of MOP algorithms is necessary and beneficial in the design process of sub-threshold CMOS logic standard cells. Optimization results are presented for an inverter, NAND gate, and NOR gate in a 65 nm process technology.

21 citations

Proceedings ArticleDOI
03 Aug 2010
TL;DR: In this paper, the authors regard the problem of sub-threshold standard cells for digital ultra-low power systems as a multiobjective optimization problem (MOP) and show that the support of MOP algorithms is necessary and beneficial in the design process of subthreshold CMOS logic standard cells.
Abstract: Transistor sizing of sub-threshold standard cells for digital ultra-low power systems is a very challenging task because robustness has to be considered as an important design objective in addition to the competing resources power consumption and propagation delay. In this paper we regard this task as a multiobjective optimization problem (MOP) and show that the support of MOP algorithms is necessary and beneficial in the design process of sub-threshold CMOS logic standard cells. Optimization results are presented for an inverter, NAND gate, and NOR gate in a 65 nm process technology.

16 citations

Proceedings ArticleDOI
19 Oct 2015
TL;DR: The development of a 65nm standard cell library designed for building highly energy-efficient digital circuits and shows an improvement in energy consumption by a factor of 9.25 with a total energy consumption of 11.7pJ per clock cycle in the subthreshold domain.
Abstract: This paper describes the development of a 65nm standard cell library designed for building highly energy-efficient digital circuits. In total 43 logic cells and 19 special cells for clock-tree synthesis and place and route purposes are implemented using a commercial 65 nm bulk technology. As a result full-chip implementation of low-power systems operating at ultra-low voltage is feasible. The benefits of this subthreshold cell design are demonstrated by synthesis and analysis of a sample circuit for supply voltages from 250 mV to 1.2 V. Power analysis at gate-level shows an improvement in energy consumption by a factor of 9.25 with a total energy consumption of 11.7pJ per clock cycle in the subthreshold domain.

9 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: The proposed level shifter circuit can convert low- voltage digital input signals into high-voltage digital output signals and achieves low-power operation because it dissipates operating current only when the input signal changes.
Abstract: This paper presents a level shifter circuit capable of handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The proposed level shifter circuit can convert low-voltage digital input signals into high-voltage digital output signals. The circuit achieves low-power operation because it dissipates operating current only when the input signal changes. Measurement results demonstrated that the circuit can convert a 0.23-V input signal into a 3-V output signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input pulse.

117 citations

Journal ArticleDOI
TL;DR: A novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion and is designed for practical applications.
Abstract: Wide-range level shifters play critical roles in ultra- low-voltage circuits and systems. Although state-of-the-art level shifters can convert a subthreshold voltage to the standard supply voltage, they may have limited operating ranges, which restrict the flexibility of dynamic voltage scaling. Therefore, this paper presents a novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion. The proposed level shifter is a hybrid structure comprising a modified Wilson current mirror and generic CMOS logic gates. The simulation and measurement results were verified using a 65-nm technology. The minimal operating voltage of the proposed level shifter was less than 200 mV based on the measurement results. In addition to the operating range, the delay, power consumption, and duty cycle of the proposed level shifter were designed for practical applications.

105 citations

Journal ArticleDOI
TL;DR: The proposed design reliably converts 180-mV input signals into 1-V output signals, while maintaining operational frequencies above 1-MHz, while taking into account process-voltage-temperature variations.
Abstract: In this brief, a new low-power level shifter (LS) is presented for robust logic voltage shifting from near/sub-threshold to above-threshold domain. The new circuit combines the multi-threshold CMOS technique along with novel topological modifications to guarantee a wide voltage conversion range with limited static power and total energy consumption. When implemented in a 90-nm technology process, the proposed design reliably converts 180-mV input signals into 1-V output signals, while maintaining operational frequencies above 1-MHz, also taking into account process-voltage-temperature variations.Post-layout simulation results demonstrate that the new LS reaches a propagation delay less than 22 ns, a static power dissipation of only 6.4 nW, and a total energy per transition of only 74 fJ for a 0.2-V 1-MHz input pulse.

102 citations

Journal ArticleDOI
TL;DR: An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage SRAM based on a flexible and extensible architecture that provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation is fabricated.
Abstract: An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

87 citations

Journal ArticleDOI
TL;DR: A power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels is presented that uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level.
Abstract: This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

82 citations