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Swagata Mandal

Researcher at Jalpaiguri Government Engineering College

Publications -  28
Citations -  494

Swagata Mandal is an academic researcher from Jalpaiguri Government Engineering College. The author has contributed to research in topics: Field-programmable gate array & Error detection and correction. The author has an hindex of 4, co-authored 26 publications receiving 389 citations. Previous affiliations of Swagata Mandal include Variable Energy Cyclotron Centre & Nanyang Technological University.

Papers
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Journal ArticleDOI

Challenges in QCD matter physics --The scientific programme of the Compressed Baryonic Matter experiment at FAIR

T. O. Ablyazimov, +602 more
TL;DR: The Compressed Baryonic Matter (CBM) experiment at FAIR will play a unique role in the exploration of the QCD phase diagram in the region of high net-baryon densities, because it is designed to run at unprecedented interaction rates.
Journal ArticleDOI

Challenges in QCD matter physics - The Compressed Baryonic Matter experiment at FAIR

T. O. Ablyazimov, +586 more
TL;DR: The Compressed Baryonic Matter (CBM) experiment at FAIR will play a unique role in the exploration of the QCD phase diagram in the region of high net-baryon densities, because it is designed to run at unprecedented interaction rates as discussed by the authors.
Journal ArticleDOI

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

TL;DR: A first of its kind methodology for novel transient fault correction using MMC for FPGAs using modified matrix code (MMC) is used for multibit error correction in FPGA-based systems, and dynamic partial reconfigurations is considered to reduce the reconfiguration time.
Proceedings ArticleDOI

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA

TL;DR: In this paper, the authors proposed a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional Erasure Product Code for error correction in the configuration memory of static random access memory (SRAM) based Field Programmable Gate Array (FPGA) devices.
Journal ArticleDOI

An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

TL;DR: A novel orthogonal concatenated code and cyclic redundancy check have been used to mitigate the effects of data corruption in the user data and a novel memory management algorithm is proposed that helps to process the data at the back-end computing nodes removing the added path delays.