Among the emerging technologies Field-Coupled devices like Quantum dot Cellular Automata are one of the most interesting. Of all the practical implementations of this principle NanoMagnet Logic shows many important features, such like a very low power consumption and the feasibility with up-to-date technology. However its working principle, based on the interaction among neighbor cells, is quite different from CMOS circuits. Dedicated design and simulation tools for this technology are necessary to further study this technology, but at the moment there are no such tools available in the scientific scenario.

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ToPoliNano: NanoMagnet Logic Circuits Design and Simulation

With the advancement of fabrication technology, devices and interconnecting wires are being placed in closer proximity and circuits are operating at higher frequencies. This results in crosstalk between overlapping wire segments. Work on routing channels with reduced crosstalk is a very important area for current research. The crosstalk minimization problem in the reserved two-layer Manhattan routing model is NP-complete, even if the channel instances are without any vertical constraints. The problem of crosstalk minimization remains NP-complete for general instances of channel specifications with both horizontal and vertical constraints. In this paper we have developed two algorithms for computing reduced crosstalk routing solutions on a given routing solution of minimum area for general instances of channel specifications. Performance of our algorithms is encouraging enough for most of the existing benchmark channels, and reduction in crosstalk for these channels is up to 28.34% for a given routing solution.

/pdf/two-algorithms-for-minimizing-crosstalk-in-two-layer-channel-3508n5aliv.pdf

Two Algorithms for Minimizing Crosstalk in Two-Layer Channel Routing

Green technology is a new research area in electronics, which meets the needs of society and explores the ability of VLSI circuits and embedded systems to positively impact the environment In VLSI physical design automation, channel routing is a fundamental problem but reducing the total wire length for interconnecting the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed Reducing the total wire length for interconnection not only minimizes the cost of the physical wire segments required, but also reduces the amount of occupied area for interconnection, signal propagation delays, electrical hazards, power consumption, heat generation, and over all the parasitics present in a circuit Thus it has a direct impact on daily life and environment Channel routing problem for wire length minimization is an NP-hard problem Hence as a part of developing an alternative, we modify the existing graph theoretic framework Track_Assignment_Heuristic (TAH) to reduce the total (vertical) wire length In this paper we propose an efficient polynomial time graph based parallel algorithm to reduce the total wire length without radically increasing of required area for interconnection in the reserved two-layer no-dogleg Manhattan channel routing model The performance and efficiency of our algorithm is highly encouraging for different well-known benchmarks channels

An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits

To trigger events for application-specific data transfer among registers in a multimillion-gate system-on-chip (SoC), various kinds of clock signals, selectively driven by different frequency-dependent sources and/or dividers (DIVs), are usually centralized in one or more clock generation modules, where clock gating cells (CGCs), multiplexers (MUXes) and DIVs are used to create the clocks required by different functional operations in an SoC. These modules will introduce uncommon and longer timing paths for clock propagations and further make the clock tree synthesis (CTS) process become more challenging due to the on-chip-variation (OCV) effects. In addition, high volume of switching activities in the increased number of clock logic cells will consume more power. In this article, a novel design platform, merging and replacing of multiple multiplexers and dividers (MRMMD), is developed to intelligently identify those suspicious clock architectures and resynthesize them into a power-and-area effective and less complicated clock structure. Using our resynthesis platform, not only the number of clock-related timing paths and their corresponding logic levels can be reduced, but also the corresponding analysis and implementations of clock skew minimizations during CTS become much easier. The experimental results implemented in TSMC 55- and 28-nm process nodes on optimizing some industrial clock architectures showed that significant reductions of area, power, latency, skew and clock path, logic level, OCV impact, total wire length, and implementation runtime are achieved using our MRMMD platform.

A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees

Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers). To be more specific, through this algorithm we convert a two-layer channel routing problem into a four-layer channel routing problem using HNCG and VCG of the channel. Next, we show the experimental results and graphical structure of that solution.

http://ieeexplore.ieee.org/iel7/6451322/6466095/06466134.pdf

A new algorithm with minimum track for four layer channel routing in VLSI design

Minimization of total (vertical) wire length is one of the most important problems in laying out blocks in VLSI physical design. Minimization of wire length not only reduces the cost of physical wiring required, but also reduces the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg, two-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as low total (vertical) wire length as possible. In this paper we develop an efficient heuristic algorithm for appreciably reducing the total wire length in the reserved two-layer no-dogleg Manhattan channel routing model. Experimental results obtained are greatly encouraging.

A graph based algorithm to minimize total wire length in VLSI channel routing

Channel routing problem is a problem in VLSI physical design whose objective is to compute a feasible minimum area routing solution. A channel is a rectangular routing region where the terminals are usually present on two of its opposite sides, and the other two sides are open ends. Routing is the task to interconnect all the nets present in a channel obeying constraints within the channel region. A net is a set of terminals that need to be electrically connected (usually using rectilinear wiring). The two important constraints present in a channel are horizontal constraint and vertical constraint. In this paper we visualize these two constraints through graphs in a different way, and combinedly use them to compute reduced area channel routing solutions.

Graphs- The Tool to Visualize the Problems in VLSI Channel Routing

The minimization of total wire length is one of the most key issue in VLSI physical design automation, as it reduces the cost of physical wiring required along with the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delay. So, it is still important as cost as well as high performance issue. The problem of reduced wire length routing solutions in no-dogleg reserved two-layer (VH) and multi-layer (ViHi, 2 ≤ i < dmax and ViHi+1, 2 ≤ i < dmax − 1) channel routing is NP-hard, so, it is interesting to develop heuristic algorithms that compute routing solutions of as minimum total (vertical) wire length as possible. Here we propose two algorithms to reduce the total (vertical) wire length in channel routing problem. First we develop an efficient re-router Further_Reduced_Wire_Length (FRWL) to optimize the wire length in the reserved two-layer (VH) no-dogleg channel routing model and then we develop an algorithm Multi-Layer_Reduced_Wire_Length (MLRWL) to minimize the total (vertical) wire length in channel routing problem in the reserved multi-layer (ViHi, 2 ≤ i < dmax and ViHi+1, 2 ≤ i < dmax − 1) no-dogleg Manhattan routing models, where vertical and horizontal layers of interconnect alternate. Experimental results computed for available benchmark instances indicate that the algorithms perform well. Keywords—Channel routing problem, Manhattan routing, No-dogleg, Parametric difference, Wire length minimization, VLSI.

A Re-router for Reducing Wire Length in Multi- Layer No-Dogleg Channel Routing

In VLSI physical design automation minimization of total (vertical) wire length is one of the most important problems as it reduces the cost of physical wiring required along with the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg reserved two- and four-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as minimum total (vertical) wire length as possible. In this paper we develop two algorithms to minimize the total (vertical) wire length in channel routing problem. First we develop an efficient re-router Further_Reduced_Wire_Length (FRWL) to optimize the wire length in the reserved two-layer (VH) no-dogleg channel routing model and then we develop a next algorithm Four_Layer_Reduced_Wire_Length (FLRWL) to optimize the total (vertical) wire length in the reserved four-layer (VHVH) no-dogleg Manhattan routing model. Experimental results computed for available benchmark instances are greatly encouraging.

Swagata Saha Sau

Papers

A graph based algorithm to minimize total wire length in VLSI channel routing

Graphs- The Tool to Visualize the Problems in VLSI Channel Routing

An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits

A Re-router for Reducing Wire Length in Multi- Layer No-Dogleg Channel Routing

A re-router for optimizing wire length in two-and four-layer no-dogleg channel routing