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Author

Swarup Bhunia

Other affiliations: Intel, Université Paris-Saclay, Purdue University  ...read more
Bio: Swarup Bhunia is an academic researcher from University of Florida. The author has contributed to research in topics: Hardware Trojan & Trojan. The author has an hindex of 43, co-authored 413 publications receiving 8867 citations. Previous affiliations of Swarup Bhunia include Intel & Université Paris-Saclay.


Papers
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Journal ArticleDOI
15 Jul 2014
TL;DR: The threat of hardware Trojan attacks is analyzed; attack models, types, and scenarios are presented; different forms of protection approaches are discussed; and emerging attack modes, defenses, and future research pathways are described.
Abstract: Security of a computer system has been traditionally related to the security of the software or the information being processed. The underlying hardware used for information processing has been considered trusted. The emergence of hardware Trojan attacks violates this root of trust. These attacks, in the form of malicious modifications of electronic hardware at different stages of its life cycle, pose major security concerns in the electronics industry. An adversary can mount such an attack with an objective to cause operational failure or to leak secret information from inside a chip-e.g., the key in a cryptographic chip, during field operation. Global economic trend that encourages increased reliance on untrusted entities in the hardware design and fabrication process is rapidly enhancing the vulnerability to such attacks. In this paper, we analyze the threat of hardware Trojan attacks; present attack models, types, and scenarios; discuss different forms of protection approaches, both proactive and reactive; and describe emerging attack modes, defenses, and future research pathways.

588 citations

Journal ArticleDOI
TL;DR: Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.
Abstract: Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.

468 citations

Book ChapterDOI
30 Aug 2009
TL;DR: A test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes that maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation.
Abstract: In order to ensure trusted in---field operation of integrated circuits, it is important to develop efficient low---cost techniques to detect malicious tampering (also referred to as Hardware Trojan ) that causes undesired change in functional behavior Conventional post--- manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side---channel approaches that monitor the impact of a Trojan circuit on power or current signature Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns

411 citations

Proceedings ArticleDOI
20 Nov 2009
TL;DR: The threat posed by hardware Trojans and the methods of deterring them are analyzed, a Trojan taxonomy, models of Trojan operations and a review of the state-of-the-art Trojan prevention and detection techniques are presented.
Abstract: Malicious modification of hardware during design or fabrication has emerged as a major security concern. Such tampering (also referred to as Hardware Trojan) causes an integrated circuit (IC) to have altered functional behavior, potentially with disastrous consequences in safety-critical applications. Conventional design-time verification and post-manufacturing testing cannot be readily extended to detect hardware Trojans due to their stealthy nature, inordinately large number of possible instances and large variety in structure and operating mode. In this paper, we analyze the threat posed by hardware Trojans and the methods of deterring them. We present a Trojan taxonomy, models of Trojan operations and a review of the state-of-the-art Trojan prevention and detection techniques. Next, we discuss the major challenges associated with this security concern and future research needs to address them.

398 citations

Journal ArticleDOI
TL;DR: This article examines the research on hardware Trojans from the last decade and attempts to capture the lessons learned and identifies the most critical lessons for those new to the field and suggests a roadmap for future hardware Trojan research.
Abstract: Given the increasing complexity of modern electronics and the cost of fabrication, entities from around the globe have become more heavily involved in all phases of the electronics supply chain. In this environment, hardware Trojans (i.e., malicious modifications or inclusions made by untrusted third parties) pose major security concerns, especially for those integrated circuits (ICs) and systems used in critical applications and cyber infrastructure. While hardware Trojans have been explored significantly in academia over the last decade, there remains room for improvement. In this article, we examine the research on hardware Trojans from the last decade and attempt to capture the lessons learned. A comprehensive adversarial model taxonomy is introduced and used to examine the current state of the art. Then the past countermeasures and publication trends are categorized based on the adversarial model and topic. Through this analysis, we identify what has been covered and the important problems that are underinvestigated. We also identify the most critical lessons for those new to the field and suggest a roadmap for future hardware Trojan research.

315 citations


Cited by
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Journal ArticleDOI
TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
Abstract: Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection.

1,227 citations

Journal ArticleDOI
Feng Pan1, Song Gao1, Chao Chen1, Cheng Song1, Fei Zeng1 
TL;DR: A comprehensive review of the recent progress in the so-called resistive random access memories (RRAMs) can be found in this article, where a brief introduction is presented to describe the construction and development of RRAMs, their potential for broad applications in the fields of nonvolatile memory, unconventional computing and logic devices, and the focus of research concerning RRAMS over the past decade.
Abstract: This review article attempts to provide a comprehensive review of the recent progress in the so-called resistive random access memories (RRAMs) First, a brief introduction is presented to describe the construction and development of RRAMs, their potential for broad applications in the fields of nonvolatile memory, unconventional computing and logic devices, and the focus of research concerning RRAMs over the past decade Second, both inorganic and organic materials used in RRAMs are summarized, and their respective advantages and shortcomings are discussed Third, the important switching mechanisms are discussed in depth and are classified into ion migration, charge trapping/de-trapping, thermochemical reaction, exclusive mechanisms in inorganics, and exclusive mechanisms in organics Fourth, attention is given to the application of RRAMs for data storage, including their current performance, methods for performance enhancement, sneak-path issue and possible solutions, and demonstrations of 2-D and 3-D crossbar arrays Fifth, prospective applications of RRAMs in unconventional computing, as well as logic devices and multi-functionalization of RRAMs, are comprehensively summarized and thoroughly discussed The present review article ends with a short discussion concerning the challenges and future prospects of the RRAMs

1,129 citations

Journal ArticleDOI
14 Jun 2014
TL;DR: This paper exposes the vulnerability of commodity DRAM chips to disturbance errors, and shows that it is possible to corrupt data in nearby addresses by reading from the same address in DRAM by activating the same row inDRAM.
Abstract: Memory isolation is a key property of a reliable and secure computing system--an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors

999 citations