Swatilekha Majumdar

Bio: Swatilekha Majumdar is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: nvSRAM & Noise reduction. The author has an hindex of 3, co-authored 9 publications receiving 18 citations.

Hybrid CMOS-OxRAM based 4T-2R NVSRAM with efficient programming scheme

Abstract: In this paper, we present an OxRAM based compact 4T-2R NVSRAM design with a novel efficient programming scheme to achieve low-power and low area footprint. 3 nm thick HfOx based OxRAM devices and 90 nm CMOS technology node were used for all simulations. Our proposed 4T-2R NVSRAM is programmed using a two cycle write process and is implemented for real-time non-volatility rather than last-bit, or power-down non-volatility. We also show that by carefully choosing the OxRAM programmed resistance levels the pull-down NMOS transitor size, and NVSRAM programming energy can be further reduced by a factor of ˜ 3x and ˜ 4x respectively.

Programming scheme based optimization of hybrid 4T-2R OxRAM NVSRAM

Abstract: In this paper, we present a novel single-cycle programming scheme for 4T-2R NVSRAM, exploiting pulse engineered input signals. OxRAM devices based on 3 nm thick bi-layer active switching oxide and 90 nm CMOS technology node were used for all simulations. The cell design is implemented for real-time non-volatility rather than last-bit, or power-down non-volatility. Detailed analysis of the proposed single-cycle, parallel RRAM device programming scheme is presented in comparison to the two-cycle sequential RRAM programming used for similar 4T-2R NVSRAM bit-cells. The proposed single-cycle programming scheme coupled with the 4T-2R architecture leads to several benefits such as- possibility of unconventional transistor sizing, 50% lower latency, 20% improvement in SNM and ~20× reduced energy requirements, when compared against two-cycle programming approach.

Stability analysis of hybrid CMOS-RRAM based 4T-2R NVSRAM

Abstract: In this paper, we study in detail the stability metrics of emerging RRAM based non-volatile SRAM (NVSRAM) architectures (4T-2R in particular). Cell stability is analyzed using parameters obtained from N-curves (WTV, WTI, SVNM, SINM), and SNM curves as defined by Seevinck [1]. Comparative analysis of all stability metrics of the 4T-2R NVSRAM architecture (90 nm CMOS, 3nm HfOx stack) with an optimized CMOS 6T SRAM architecture (90 nm node) is performed at bitcell level. While for resistive NVSRAM SINM improves by 18%, the cell SVNM and WTV degrade by 11% and 4% respectively. Effect of RRAM variability on the overall cell stability is also studied.

Single Bit-Line Differential Sensing Based Real-Time NVSRAM for Low Power Applications

Abstract: In this brief, we present a novel single bit-line differential programming scheme for 4T-2R NVSRAM. The NVSRAM presented in this brief not only uses an unconventional scheme of using differential sensing using a single bit-line, without the use of access transistors, but also leads an alternative transistor sizing approach for sizing the access and pull down transistors to improve write margins. The NVSRAM design used in this brief constitutes of two 3nm thick HfOx based OxRAM devices and four transistors designed at 90 nm CMOS technology node. The cell design is implemented for real-time non-volatility rather than last-bit non-volatility. Detailed analysis of the proposed single bit-line technique with parallel RRAM device programming scheme is presented in comparison to the previous NVSRAM programming schemes used for similar 4T-2R NVSRAM bit-cells.

Efficient Video Summarization Framework using EEG and Eye-tracking Signals.

Abstract: This paper proposes an efficient video summarization framework that will give a gist of the entire video in a few key-frames or video skims. Existing video summarization frameworks are based on algorithms that utilize computer vision low-level feature extraction or high-level domain level extraction. However, being the ultimate user of the summarized video, humans remain the most neglected aspect. Therefore, the proposed paper considers human's role in summarization and introduces human visual attention-based summarization techniques. To understand human attention behavior, we have designed and performed experiments with human participants using electroencephalogram (EEG) and eye-tracking technology. The EEG and eye-tracking data obtained from the experimentation are processed simultaneously and used to segment frames containing useful information from a considerable video volume. Thus, the frame segmentation primarily relies on the cognitive judgments of human beings. Using our approach, a video is summarized by 96.5% while maintaining higher precision and high recall factors. The comparison with the state-of-the-art techniques demonstrates that the proposed approach yields ceiling-level performance with reduced computational cost in summarising the videos.

Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM

Abstract: Resistive random access memories (RRAMs) feature high-speed operations, low-power consumption, and nonvolatile retention, thus serving as a promising candidate for future memory applications. To explore the applications of the RRAM, switching variability and cycling endurance need to be addressed. This paper presents extensive characterizations of multi-kb RRAM arrays during forming, set, reset, and cycling operations. The relationships among programming conditions, memory window, and endurance features are presented. The experimental results are then used to perform variability-aware simulations of a 128-bit RRAM-based ternary content-addressable-memory (TCAM) macro. The tradeoff among endurance, search latency, and reliability in terms of match/mismatch detection is explored, identifying the programming conditions that allow to obtain a searching speed comparable to static random access memory-based TCAMs (2 ns on average and 3 ns at $3\sigma $ ) while guaranteeing good reliability metrics (with a time ratio of 3000 on average and 150 at $3\sigma $ ).

Role of oxygen vacancies in Cr-doped SrTiO3 for resistance-change memory

Abstract: Transition-metal oxides exhibiting a bistable resistance state are attractive for non-volatile memory applications. The relevance of oxygen vacancies (VO) for the resistance-change memory was investigated with x-ray fluorescence, infrared microscopy, and x-ray absorption spectroscopy using Cr-doped SrTiO3 as example. We propose that the microscopic origin of resistance switching in this class of materials is due to an oxygen-vacancy drift occurring in close proximity to one of the electrodes.

RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications

Abstract: Static Random-Access Memories (SRAMs) have flourished in the memory market relying on their speed, power consumption and compatibility with standard CMOS process technology. Conventional SRAMs are characterized by volatility, limiting their role in applications where non-volatility is essential. Non-Volatile SRAMs (NVSRAMs) represent an appealing solution, where Resistive RAM (RRAM) can act as a non-volatile element for SRAM. RRAM relies on the basic physical phenomenon of operation called resistive switching. This paper presents different NVSRAM structures, while exploring their principle of operation. Also, a comparison in terms of area, speed, power consumption and design complexity is presented for three NVSRAM memory cells implemented in a 130-nm high voltage CMOS technology from STMicroelectronics.

ReplayCache: Enabling Volatile Cachesfor Energy Harvesting Systems

Abstract: Energy harvesting systems have shown their unique benefit of ultra-long operation time without maintenance and are expected to be more prevalent in the era of Internet of Things. However, due to the batteryless nature, they suffer unpredictable frequent power outages. They thus require a lightweight mechanism for crash consistency since saving/restoring checkpoints across the outages can limit forward progress by consuming hard-won energy. For the reason, energy harvesting systems have been designed with a non-volatile memory (NVM) only. The use of a volatile data cache has been assumed to be not viable or at least challenging due to the difficulty to ensure cacheline persistence. In this paper, we propose ReplayCache, a software-only crash consistency scheme that enables commodity energy harvesting systems to exploit a volatile data cache. ReplayCache does not have to ensure the persistence of dirty cachelines or record their logs at run time. Instead, ReplayCache recovery runtime re-executes the potentially unpersisted stores in the wake of power failure to restore the consistent NVM state, from which interrupted program can safely resume. To support store replay during recovery, ReplayCache partitions program into a series of regions in a way that store operand registers remain intact within each region, and checkpoints all registers just before power failure using the crash consistency mechanism of the commodity systems. For performance, ReplayCache enables region-level persistence that allows the stores in a region to be asynchronously persisted until the region ends, exploiting ILP. The evaluation with 23 benchmark applications show that compared to the baseline with no caches, ReplayCache can achieve about 10.72x and 8.5x-8.9x speedup (on geometric mean) for the scenarios without and with power outages, respectively.

Non-volatile SRAM memory cells based on ReRAM technology

Abstract: Static Random-Access Memories (SRAMs) are very common in today’s chip industry due to their speed and power consumption but are classified as volatile memories. Non-volatile SRAMs (nvSRAMs) combine SRAM features with non-volatility. This combination has the advantage to retain data after power off or in the case of power failure, enabling energy-efficient and reliable systems under frequent power-off conditions. In this work, several nvSRAMs architectures based on Oxide Random-Access Memory (OxRAM) technology are presented and compared. OxRAMs are non-volatile memories considered as a subset of Resistive RAM (ReRAM) technology.