Sweety Dabas

Bio: Sweety Dabas is an academic researcher from Maharaja Surajmal Institute of Technology. The author has contributed to research in topics: Equivalent circuit & Electrical element. The author has an hindex of 2, co-authored 9 publications receiving 22 citations.

Simulation of voltage based efficient fire sensor on FPGA using SSTL IO standards

Abstract: In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL)IO standards. Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit. In this work we have taken two values for LFM i.e. 250, 500 and three profiles for heat sink are taken, these are low profile, medium profile and high profile. When the voltage sensor is operating at 1THz and LFM is 250 with low profile heat sink, junction temperature of SSTL135_DCI is reduced up to 5.12% 6.03% and 20.77% as compared to SSTL12, SSTL12_DCI and SSTL135_R respectively. Under same operating frequency and heat sink profile with LFM as 500, we are achieving 3.69%, 5.22% and 17.99% less junction power reduction in SSTL135_DCI with respect to SSTL12, SSTL12_DCI and S S TL135_Rrespectively. This design is implemented on Kintex-7 FPGA, XC7K70T device and −3 speed grades. In this work we have used Verilog as HDL and Xilinx ISE 14.6 as simulator.

Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA

Abstract: This paper illustrates the behavior of the UART in response to the various I/O standards. Research has been carried out to find out the most ideal standard for UART design which would thereby minimize the losses. Increase in power is seen as the frequency and capacitance for a standard are increased. When a relative analysis is done for the different I/O standards, it has been found out that LVCMOS18 consumes the least power and hence is the most efficient I/O standard for the UART design. Increment in power consumption has been observed within a percentage of 99.73–40% for a capacitance of 5 pF and 99.64–54.54% for a capacitance value of 50 pF. XILINX software and Verilog Hardware Description Language have been used for this purpose. The behavior for various standards has been studied to get the most energy-efficient design for the UART. This would help in increasing the output from the UART, thereby proving to be a boon in the field of electronics where power consumption is a major issue.

Future Perspective and Current Aspects of Internet of Things Enable Design

Abstract: In this work, we are going to survey the latest progress in Internet of Things (IoTs) and also design IoTs enable electronics design like frame buffer, content addressable memory, and key generator for encr4yption and decryption. We are analyzing future perspective, overall impact, and its role in every corner of life, characteristics features and current aspects of IoTs. Apart from this, we study how this concept came into existence and its emergence changes our lives. In this paper, we have also designed IoTs enable Frame Buffer on FPGA for Object Tracking, IoTs enable Content Addressable Memory for processor and IoTs enable Key Generator for Green Communication. In order to make IOTs enable design, we are embedding a 128-bit Internet Protocol Version 6 (IPv6) address in each and every design that enables.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

Abstract: In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.

Energy Efficient Counter Design Using Voltage Scaling on FPGA

Abstract: In this work, we are using voltage scaling to make the counter design as an energy efficient design. The 74163 counter is a 4-bit fully synchronous counter that is available in both TTL and CMOS logic families. In addition to performing the counting function, it can be cleared or loaded in parallel. It has been observed that when different powers have been measured at different frequencies and different voltages in case of counter the significant power dissipation is in case clocks and IOs. Out of which in case of clock the maximum power dissipation is in range of 12.126W to 35.056W at which is in case of 1THz when measured at different voltage levels where as in case of IOs the maximum power dissipation is in range of 20.636W to 25.031W. Which is again in case of 1THz when measured at different voltage levels. There is not much significant change in case of signal and leakage power at different voltage levels. The maximum total power dissipation is in range of 33.887W to 67.986W at frequency of 1THz when operated at different voltages. Also there can be 94.45% to 99.61% reduction in total power dissipation if we operate on frequency of 1MHz instead of frequency of 1THz at different Voltage levels.

SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Abstract: Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.

A Discussion about Upgrading the Quick Script Platform to Create Natural Language based IoT Systems

Abstract: Objectives: With the advent of AI and IoT, the idea of incorporating smart things/appliances in our day to day life is converting into a reality. The paper discusses the possibilities and potential of designing IoT systems which can be controlled via natural language, with help of Quick Script as a development platform. Methods/Statistical Analysis: Quick Script (or QS) is an open-source, easy to learn tool made by our team of student developers for programming virtual conversational entities. This paper focuses on a discussion about how some improvements can be made in the underlying implementation of QS and the resulting uncomplicated and simple platform which can be used to create natural language based IoT systems. It explores the architecture/design pattern required for creating such systems. Findings: This exploration reveals how the idea of turning a simple NLP tool to handling IoT systems can be implemented, and where all the necessary changes/ additions are to be made. The benefits of this will include sharing the power of controlling and even programming (up to some extent) to the user end. As well as providing a simple intermediary to make communication between man and his machines a little more natural. Application/Improvements: It has always been a fantasy in movies to have appliances and gadgets work according to our speech inputs in real time. We humans have always tried to take complete advantage of technologies for living better and working more productively. The idea behind this paper drives for the same cause. Applications of any natural language based service can be endless–ranging from home to industry. With the speech based interaction, this will even help the physically disabled people.

Energy efficient flip flop design using voltage scaling on FPGA

Abstract: In this work, we are using voltage scaling and frequency scaling In voltage scaling, voltage is scaled from 3V to 1V, where intermediate values are 25V, 2V, 18V and 15V In frequency scaling, frequency is scaled from 1 MHz to 1 THz, where intermediate values are 10 MHz, 100 MHz, 1 GHz, 10 GHz and 100 GHz When we scale down device operating frequencies from 1THz to 1GHz, there is 729% reduction in power dissipation on Virtex-6 FPGA When we scale down device operating frequencies from 1THz to 1GHz, there is 9875% reduction in power dissipation on Virtex-4 FPGA When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 8223%, 9683%, 9845% and 99% reduction in power dissipation respectively on Virtex-6 FPGA on 10MHz device operating frequency When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 7442%, 9267%, 9471% and 9766% reduction in power dissipation respectively on Virtex-6 FPGA on 1THz device operating frequency