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Syed Ershad Ahmed

Bio: Syed Ershad Ahmed is an academic researcher from Birla Institute of Technology and Science. The author has contributed to research in topics: Multiplier (economics) & Adder. The author has an hindex of 6, co-authored 26 publications receiving 103 citations.

Papers
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Proceedings ArticleDOI
10 Jul 2016
TL;DR: The authors present a method which combines the Mitchell's approximation and hardware truncation scheme in a novel way resulting in an iterative multiplier with improved precision and area, which significantly reduce the overall hardware requirement of the multiplier.
Abstract: Recent studies have demonstrated the potential for achieving higher area and power saving with approximate computation in error tolerant applications involving signal and image processing. Multiplication is a major mathematical operation in these applications which when performed in logarithmic number system results in faster and energy efficient design. In this paper, the authors present a method which combines the Mitchell's approximation and hardware truncation scheme in a novel way resulting in an iterative multiplier with improved precision and area. Further, proposed truncation approach and fractional predictor significantly reduce the overall hardware requirement of the multiplier. Experimental results prove the superiority of the proposed multiplier over previous designs.

22 citations

Proceedings ArticleDOI
07 Jan 2012
TL;DR: Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.
Abstract: This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This 'self-reconfigurable' property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.

19 citations

Proceedings ArticleDOI
19 Aug 2012
TL;DR: The proposed 64-bit comparator design results in 63% reduced quantum delay, 21% reduction quantum cost and 16% reduced garbage outputs when compared with the best existing design of tree based comparator.
Abstract: This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. The proposed reversible comparator design consists of three stages. The first stage consists of a 1-bitcomparator where two outputs, gi indicating Ai > Bi and eiindicating Ai = Bi, are generated for ith operand bits. The outputs of 1-bit comparator stage are grouped in the second stage using prefix grouping and the final outputs G indicating A > B and E indicating A=B are generated. In the last stage the outputs of second stage i.e. G and E are used to generate Lsignal indicating A

18 citations

Journal ArticleDOI
TL;DR: This letter proposes an unsigned approximate multiplier architecture segmented into three portions: the least significant portion that contributes least to the partial product (PP) is replaced with a new constant compensation term to improve hardware savings without sacrificing accuracy.
Abstract: This paper proposes an unsigned approximate multiplier architecture segmented into three portions; the least significant portion that contributes least to the partial product is replaced with a new constant compensation term to improve hardware savings without sacrificing accuracy. The partial products in the middle portion are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple yet efficient error correction module. The most significant portion of the multiplier is implemented using exact logic as approximating it will results in a large error. Experimental results of 8-bit multiplier show that power and power-delay products are reduced up to 47.7% and 55.2% respectively in comparison with the exact design and 36.9% and 39.5% respectively in comparison with the existing designs without significant compromise on accuracy.

16 citations

Journal ArticleDOI
01 Jun 2019
TL;DR: The authors describe a technique that combines Mitchell’s approximation with a novel hardware truncation scheme resulting in an iterative multiplier with improved precision and reduced area that significantly reduces the overall hardware cost of the multiplier.
Abstract: As the modern computing systems become increasingly embedded and portable, a growing set of applications in media processing (graphics, audio, video, and image) has evolved. Multiplication is the operation that is most often used in these applications which when accomplished in logarithmic number system results in an area efficient and faster design. In this work, the authors describe a technique that combines Mitchell's approximation with a novel hardware truncation scheme resulting in an iterative multiplier with improved precision and reduced area. Further, a new fractional predictor combined with an existing truncated logarithmic shifter significantly reduces the overall hardware cost of the multiplier. Simulations carried out on benchmark image processing applications such as Lena, cameraman and pirate clearly indicate that the proposed technique performs better than those available in the literature.

14 citations


Cited by
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Journal ArticleDOI
TL;DR: The designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance and it is found that the proposed approximate LMs with an appropriate number of inexact bits achieve higher accuracy and lower power consumption than conventional LMs using exact units.
Abstract: In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance. Non-iterative ALMs, that use three inexact mantissa adders, are presented. The proposed iterative ALMs (IALMs) use a set-one adder in both mantissa adders during an iteration; they also use lower-part-or adders and approximate mirror adders for the final addition. Error analysis and simulation results are also provided; it is found that the proposed approximate LMs with an appropriate number of inexact bits achieve higher accuracy and lower power consumption than conventional LMs using exact units. Compared with conventional LMs with exact units, the normalized mean error distance of 16-bit approximate LMs is decreased by up to 18% and the power-delay product has a reduction of up to 37%. The proposed approximate LMs are also compared with previous approximate multipliers; it is found that the proposed approximate LMs are best suitable for applications allowing larger errors, but requiring lower energy consumption. Approximate Booth multipliers fit applications with less stringent power requirements, but also requiring smaller errors. Case studies for error-tolerant computing applications are provided.

109 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed an 8-point DCT approximation that requires only 14 addition operations and no multiplications, compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio.
Abstract: Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology.

107 citations

Book
01 Jan 1984
TL;DR: This is a modern revision of the classic digital design textbook that teaches the basic tools for the design of digital circuits in a clear, easily accessible manner and is accompanied by Verilog simulator software>SynaptiCAD's VeriLogger Pro evaluation version.
Abstract: From the Publisher: This is a modern revision of the classic digital design textbook. The book teaches the basic tools for the design of digital circuits in a clear, easily accessible manner. New to This Edition: Nine sections on Verilog Hardware Description Language (HDL) inserted in discrete sections, allowing the material to be covered or skipped as desired. The Verilog HDL presentation is at a suitable level for beginning students who are learning digital circuits for the first time. Reorganized material on combinational circuits is now covered in a single chapter. The emphasis in the sequential circuits chapters is now on design with D flip-flops instead of JK and SR flip-flops. The material on memory and programmable logic is now consolidated in one chapter. Chapter 8 consists mostly of new material and now covers digital design in the Register Transfer Level (RTL), preparing the reader for more advanced design projects and further Verilog HDL studies. A new section in Chapter 11 supplements the laboratory experiments with HDL experiments. These enable the reader to check the circuits designed in the laboratory by means of hardware components and/or by HDL simulation. Text accompanied by Verilog simulator software>SynaptiCAD's VeriLogger Pro evaluation version, a Verilog simulation environment that combines all of the features of a traditional Verilog simulator with a powerful graphical test vector generator. Fast model testing in VeriLogger Pro allows the reader to perform bottom-up testing of every model in a design. All of the HDL examples in thebook can be found on the CD-ROM. A Companion Website includes resources for instructors and students such as transparency masters of all figures in the book, all HDL code examples from the book, a Verilog tutorial, tutorials on using the VeriLogger Pro software, and more. CONTENTS Binary Systems Boolean Algebra and Logic Gates Gate-Level Minimization Combinational Logic Synchronous Sequential Logic Registers and Counters Memory and Programmable Logic Register Transfer Level Asynchronous Sequential Logic Digital Integrated Circuits Laboratory Experiments Standard Graphic Symbols

50 citations

Journal ArticleDOI
TL;DR: An energy-efficient approximate multiplier which combines radix-4 Booth encoding and logarithmic product approximation and a datapath pruning technique is proposed and studied to reduce the hardware complexity of the multiplier.
Abstract: This paper proposes an energy-efficient approximate multiplier which combines radix-4 Booth encoding and logarithmic product approximation. Additionally, a datapath pruning technique is proposed and studied to reduce the hardware complexity of the multiplier. Various experiments were conducted to evaluate the multiplier’s error performance and efficiency in terms of energy and area utilization. The reported results are based on simulations using TSMC-180nm. Also, the applicability of the proposed multiplier is examined in image sharpening and convolutional neural networks. The applicability assessment shows that the proposed multiplier can replace an exact multiplier and deliver up to a 75% reduction in energy consumption and up to a 50% reduction in area utilization. Comparative analysis with the state-of-the-art multipliers indicates the potential of the proposed approach as a novel design strategy for approximate multipliers. When compared to the state-of-the-art approximate non-logarithmic multipliers, the proposed multiplier offers smaller energy consumption with the same level of applicability in image processing and classification applications. On the other hand, some state-of-the-art approximate logarithmic multipliers exhibit lower energy consumption than the proposed multiplier but deliver significant performance degradation for the selected application cases.

34 citations

Journal ArticleDOI
TL;DR: This work presents novel multi-bit quantum comparators to realize quantum image binarization, a basic operation to change each image pixel into black or white, named as a binary image.
Abstract: Quantum image processing has attracted much attention since it offers a potential solution to efficiently calculate some hard problems much faster than classical image processing. In particular, it is a basic operation to change each image pixel into black or white, named as a binary image. Here we present novel multi-bit quantum comparators to realize quantum image binarization. These comparators compare two quantum logic states and identify which of them is the largest. We analyze the superior performance of our proposed comparators in terms of quantum cost, quantum delay and auxiliary bits compared with the existing comparators. Furthermore, our quantum image binarization exploits the advantages of our proposed multi-bit comparators to change the values of image pixels into 0 or 255.

24 citations