Szu-Wei Huang

Bio: Szu-Wei Huang is an academic researcher from National Taiwan University. The author has contributed to research in topics: Oxide & High-κ dielectric. The author has an hindex of 6, co-authored 9 publications receiving 146 citations.

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

Abstract: A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated.

Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation

Abstract: MOS capacitors with an ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric were fabricated on n-type 4H-SiC. Al/sub 2/O/sub 3/ was prepared by room-temperature nitric acid (HNO/sub 3/) oxidation of ultrathin Al film followed by furnace annealing. The effective dielectric constant of k/spl sim/9.4 and equivalent oxide thickness of 26 /spl Aring/ are produced, and the interfacial layer and carbon clusters are not observed in this paper. The electrical responses of MOS capacitor under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12/spl plusmn/0.13 eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and limited by the minority carrier generation rate. The feasibility of integrating alternative gate dielectric on SiC by a low thermal budget process is demonstrated.

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

Abstract: A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.

Lateral nonuniformity of effective oxide charges in MOS capacitors with Al/sub 2/O/sub 3/ gate dielectrics

Abstract: The high-frequency Terman's method for interface-trap-density (D it) extraction is used to examine the lateral nonuniformity (LNU) of effective oxide charges in MOS capacitors. The two-parallel-subcapacitor model is constructed to simulate LNU charges, and it was shown that the value of the found effective Dit appears negative as the LNU occurs in the gate oxide. This technique was first used to examine the effective oxide charge distribution in Al2O3 high-k gate dielectrics prepared by anodic oxidation and nitric-acid oxidation. It was found that the LNU effect in Al2O3 is sensitive to oxidation mechanisms and can be avoided by using an appropriate oxidation process. The proposed technique is useful for the preparation and reliability improvement of high-k gate dielectrics

Method for forming metal oxide layer by nitric acid oxidation

Abstract: A method for forming a metal oxide layer by a nitric acid oxidation is disclosed. The method comprises steps of: a) providing a substrate, b) forming an ultra-thin silicon dioxide layer on the substrate, c) forming a metal layer on the silicon dioxide layer, d) oxidizing the metal layer into the metal oxide layer by the nitric acid oxidation, and e) annealing the metal oxide layer.

Method for making a semiconductor device having a high-k gate dielectric

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Electrical performance of Al2O3 gate dielectric films deposited by atomic layer deposition on 4H-SiC

Abstract: Stoichiometric and pure Al2O3 gate dielectric films were grown on n-type 4H-SiC by a thermal atomic layer deposition process. The electrical properties of both amorphous and epitaxial Al2O3 films were studied by capacitance-voltage and current-voltage measurements of metal-oxide-semiconductor capacitors. A dielectric constant of 9 and a flatband voltage shift of +1.3V were determined. A leakage current density of 10−3A∕cm2 at 8MV∕cm was obtained for the amorphous Al2O3 films, lower than that of any high-κ gate oxide on 4H-SiC reported to date. A Fowler-Nordheim tunneling mechanism was used to determine an Al2O3∕4H-SiC barrier height of 1.58eV. Higher leakage current was obtained for the epitaxial γ-Al2O3 films, likely due to grain boundary conduction.

Current conduction mechanisms in atomic-layer-deposited HfO2/nitrided SiO2 stacked gate on 4H silicon carbide

Abstract: In this paper, current conduction mechanisms of an atomic-layer-deposited HfO2 gate stacked on different thicknesses of thermally nitrided SiO2 based on n-type 4H SiC have been investigated and analyzed. Current-voltage and high-frequency capacitance-voltage measurements conducted at various temperatures (25−140 °C) were performed in metal-oxide-semiconductor test structures with 13 nm thick HfO2 stacked on 0-, 2-, 4-, or 6 nm thick nitrided SiO2. Various conduction mechanisms, such as Schottky emission, Fowler-Nordheim tunneling, Poole-Frenkel emission, and space-charge-limited conduction, have been systematically evaluated. The mechanisms of the current conducted through the oxides were affected by the thickness of the nitrided oxide and the electric field applied. Finally, current conduction mechanisms that contributed to hard and soft dielectric breakdown have been proposed.

Work-Function-Tuned TiN Metal Gate FDSOI Transistors for Subthreshold Operation

Abstract: The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction in Cgd, and 55% reduction in Vt variation when compared with conventional transistors, although significant short-channel effects are observed.

Electron blocking layers for electronic devices

Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.