T. Engbersen

Bio: T. Engbersen is an academic researcher. The author has contributed to research in topics: Transmission delay & Packet switching. The author has an hindex of 1, co-authored 1 publications receiving 120 citations.

Technologies and building blocks for fast packet forwarding

Abstract: We provide a review of the state of the art and the future of packet processing and switching. The industry's response to the need for wire-speed packet processing devices whose function can be rapidly adapted to continuously changing standards and customer requirements is the concept of special programmable network processors. We discuss the prerequisites of processing tens to hundreds of millions of packets per second and indicate ways to achieve scalability through parallel packet processing. Tomorrow's switch fabrics, which will provide node-internal connectivity between the input and output ports of a router or switch, will have to sustain terabit-per-second throughput. After reviewing fundamental switching concepts, we discuss architectural and design issues that must be addressed to allow the evolution of packet switch fabrics to terabit-per-second throughput performance.

Multi-protocol and multi-format stateful processing

Abstract: A system and method of processing data in a stateful protocol processing system (“SPPS”) configured to process a multiplicity of flows of messages is disclosed herein. The method includes receiving a first plurality of messages belonging to a first of the flows comporting with a first stateful protocol. In addition, a second plurality of messages belonging to a second of the flows comporting with a second stateful protocol are also received. Various events of at least first and second types associated with the first flow are then derived from the first plurality of received messages. The method further includes assigning a first protocol processing core to process the events of the first type in accordance with the first stateful protocol. A second protocol processing core is also assigned to process the events of the second type in accordance with the first stateful protocol.

Switching arrangement and method with separated output buffers

Abstract: The invention proposes a switching arrangement for transporting data packets from input ports of a switching device to output ports thereof. The data packets comprise a payload. The switching device is able to route the arriving data packets according to data packet destination information to at least one dedicated of the output ports. The switching arrangement comprises for each set of input ports in the switching device a set of output buffers. Such a set of input ports may comprise one or several input ports. The set of output buffers comprises for each set of output ports an output buffer for storing at least the payload of each data packet arriving at the corresponding input port, belonging to the set of input ports, at an address in at least those of the output buffers which pertain to the same set of output buffers, and which belong to the dedicated output ports. A set of output ports may comprise one or several output ports. For at least one of the output buffers a set of output queues is arranged which comprises for each output port an output queue, for storing therein, sorted according to the data packet destination information, the address of each payload stored in the corresponding output buffer. For the output queues which pertain to the same output port an arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the stored payloads from the output buffers to the output ports.

High speed network processor

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

NpBench: a benchmark suite for control plane and data plane applications for network processors

Abstract: Modern network interfaces demand highly intelligent traffic management in addition to the basic requirement of wire speed packet forwarding. Several vendors are releasing network processors in order to handle these demands. Network workloads can be classified into data plane and control plane workloads, however most network processors are optimized for data plane. Also, existing benchmark suites for network processors primarily contain data plane workloads, which perform packet processing for a forwarding function. We present a set of benchmarks, called NpBench, targeted towards control plane (e.g., traffic management, quality of service, etc.) as well as data plane workloads. The characteristics of NpBench workloads, such as instruction mix, parallelism, cache behavior and required processing capability per packet, are presented and compared with CommBench, an existing network processor benchmark suite [T. Wolf et. al., (2000)]. We also discuss the architectural characteristics of the benchmarks having control plane functions, their implications to designing network processors and the significance of instruction level parallelism (ILP) in network processors.

IP router architectures: an overview

Abstract: In the emerging environment of high performance IP networks, it is expected that local and campus area backbones, enterprise networks, and internet service providers (ISPs) will use multigigabit and terabit networking technologies where IP routers will be used not only to interconnect backbone segments but also to act as points of attachments to high performance wide area links. Special attention must be given to new powerful architectures for routers in order to play that demanding role. In this paper, we identify important trends in router design and outline some design issues facing the next generation of routers. It is also observed that the achievement of high throughput IP routers is possible if the critical tasks are identified and special purpose modules are properly tailored to perform them. Copyright © 2001 John Wiley & Sons, Ltd.