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T. H. Chan

Bio: T. H. Chan is an academic researcher from GlobalFoundries. The author has contributed to research in topics: JEDEC memory standards & Computer science. The author has an hindex of 2, co-authored 4 publications receiving 62 citations.

Papers
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Proceedings ArticleDOI
01 Jun 2017
TL;DR: An unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array with full array functionality, process uniformity and reliability, and 10 years data retention at 125C with extended endurance to ∼ 107 cycles is presented.
Abstract: Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array. Key features are full array functionality with low BER (bit error rate), process uniformity and reliability, 10 years data retention at 125C with extended endurance to ∼ 107 cycles. All achieved with standard BEOL process temperatures. Data retention post 260°C solder reflow temperature cycle is demonstrated.

43 citations

Proceedings ArticleDOI
18 Jun 2018
TL;DR: A fully functional embedded MRAM macro integrated into a 22-nm FD-SOI CMOS platform and showing intrinsic stand-by magnetic immunity of 1.4 kOe reveals that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.
Abstract: We demonstrate a fully functional embedded MRAM (eMRAM) macro integrated into a 22-nm FD-SOI CMOS platform. This macro combined with eFlash-flavor MTJ film stacks shows median-die bit error rate (BER) < 1 ppm after 5× solder reflows. It also meets the automotive grade-1 data retention requirement and shows intrinsic stand-by magnetic immunity of 1.4 kOe (BER criteria = 1 ppm) after 1-hr exposure at 25 °C. The results reveal that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.

24 citations

Proceedings ArticleDOI
12 Dec 2020
TL;DR: In this paper, the authors demonstrate highly reliable and mass-production ready 22nm FD-SOI 40Mb embedded-MRAM for industrial-grade (-40~125°C) applications.
Abstract: We demonstrate highly reliable and mass-production ready 22nm FD-SOI 40Mb embedded-MRAM for industrial-grade (-40~125°C) applications. This technology having 5x solder reflows compatibility stack has passed JEDEC standard qualification (ECC-OFF) with total reliability failures below the product life-time bit-failure-rate requirement for industrial-grade. Using design-process co-optimization, we show the extended performance to meet -40~150°C product operation for Auto-Grade-1 applications with stable read performance, ~47% reduced read power, data retention of 20yrs (0.1 PPM), read disturb rate of <1 PPM for ~1M cycles with 500Oe field, 1M endurance cycles, and stand-by magnetic immunity (SMI) of ~1400Oe at 25°C and ~500Oe at 150°C (0.1 PPM). With magnetic shield-in package solution, we demonstrate ~4kOe SMI at 25°C for 48hrs of field exposure.

17 citations

Proceedings ArticleDOI
12 Dec 2020
TL;DR: In this paper, the authors demonstrate superior data retention of 1 month at 125°C with improved switching efficiency at 10 ns write time without back-hopping failure and showed an engineering pathway how advanced MTJ stack engineering can improve key device parameters.
Abstract: We demonstrate superior data retention of 1 month at 125°C with improved switching efficiency at 10 ns write time without back-hopping failure. The 40Mb macro having the advanced MTJ stacks show wide operating temperature range from -40 to 125°C with the read margin even up to 150°C and zero fail bit count with ECC on. Our study indicates that the tight switching voltage distribution and the coherent switching are essential not only for fast switching but also back-hopping margin improvement. Furthermore, our paper shows an engineering pathway how advanced MTJ stack engineering can improve key device parameters.

11 citations

Proceedings ArticleDOI
01 Mar 2022
TL;DR: In this article , the authors present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate.
Abstract: We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet >1M cycles with solder reflows and path towards achieving >E12 cycles for cache applications.

2 citations


Cited by
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Journal ArticleDOI
18 Aug 2020
TL;DR: In this article, the potential of spintronics in four key areas of application (memory, sensors, microwave devices, and logic devices) is examined and the challenges that need to be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms.
Abstract: Spintronic devices exploit the spin, as well as the charge, of electrons and could bring new capabilities to the microelectronics industry However, in order for spintronic devices to meet the ever-increasing demands of the industry, innovation in terms of materials, processes and circuits are required Here, we review recent developments in spintronics that could soon have an impact on the microelectronics and information technology industry We highlight and explore four key areas: magnetic memories, magnetic sensors, radio-frequency and microwave devices, and logic and non-Boolean devices We also discuss the challenges—at both the device and the system level—that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms This Review Article examines the potential of spintronics in four key areas of application —memories, sensors, microwave devices, and logic devices — and discusses the challenges that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms

417 citations

Journal ArticleDOI
TL;DR: The suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed.
Abstract: In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I-V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed.

145 citations

Journal ArticleDOI
TL;DR: The technology that enabled present toggle and STT-MRAM products, future STT, and new MRAM technologies beyond STT are reviewed.
Abstract: Magnetoresistive random access memory (MRAM) is regarded as a reliable persistent memory technology because of its long data retention and robust endurance. Initial MRAM products utilized toggle mode writing of a balanced synthetic antiferromagnet (SAF) free layer to overcome problems with half-selected bits that challenged traditional Stoner–Wohlfarth switching. With the development of spin transfer torque (STT) switching in perpendicular magnetic tunnel junctions, the capability for scaling MRAM products increased markedly, enabling a 1-Gb device in 2019. Ongoing research will allow scaling to even higher capacities. Compared to traditional memories, STT-MRAM can save power, improve performance, and enhance system data integrity, which supports the growing computing demands for everything from data centers to Internet of Things (IoT) devices. This article provides a review of the technology that enabled present toggle and STT-MRAM products, future STT-MRAM products, and new MRAM technologies beyond STT.

92 citations

Journal ArticleDOI
TL;DR: Carbon nanomaterials have greatly advanced nonvolatile memory technology as mentioned in this paper, including memory electrodes, interfacial engineering layers, memory selectors and resistive-switching media.
Abstract: Carbon nanomaterials have greatly advanced non-volatile memory technology. In this Review, applications of various carbon nanomaterials as memory electrodes, interfacial engineering layers, memory selectors and resistive-switching media are discussed in the context of emerging non-volatile memory devices.

84 citations

Journal ArticleDOI
01 Jan 2019
TL;DR: System-level energy-delay product of common implementations of abundant-data workloads improves by three orders of magnitude in the N3XT compared with conventional architectures, which impact a broad range of application workloads and architecture configurations, from embedded systems to the cloud.
Abstract: The world’s appetite for analyzing massive amounts of structured and unstructured data has grown dramatically. The computational demands of these abundant-data applications, such as deep learning, far exceed the capabilities of today’s computing systems and are unlikely to be met with isolated improvements in transistor or memory technologies, or integrated circuit architectures alone. To achieve unprecedented functionality, speed, and energy efficiency, one must create transformative nanosystems whose architectures are based on the salient properties of the underlying nanotechnologies. Our Nano-Engineered Computing Systems Technology (N3XT) approach makes such nanosystems possible through new computing system architectures leveraging emerging device (logic and memory) nanotechnologies and their dense 3-D integration with fine-grained connectivity to immerse computing in memory and new logic devices (such as carbon nanotube field-effect transistors for implementing high-speed and low-energy logic circuits) as well as high-density nonvolatile memory (such as resistive memory), and amenable to ultradense (monolithic) 3-D integration of thin layers of logic and memory devices that are fabricated at low temperature. In addition, we explore the use of several device and integration technologies in the N3XT beyond the specific ones mentioned earlier that are also used in our main nanosystem prototypes. We also present an efficient resiliency technique to overcome endurance challenges in certain resistive memory technologies. N3XT hardware prototypes demonstrate the practicality of our architectures. We evaluate the benefits of the N3XT using a simulation framework calibrated using experimental measurements. System-level energy-delay product of common implementations of abundant-data workloads improves by three orders of magnitude in the N3XT compared with conventional architectures. These improvements impact a broad range of application workloads and architecture configurations, from embedded systems to the cloud.

83 citations