Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.

Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on the die based on an unsystematic or ad hoc approach. In this way, large decoupling capacitors are often placed at a significant distance from the current load, compromising the signal integrity of the system. This issue of power delivery cannot be alleviated by simply increasing the size of the on-chip decoupling capacitors. To be effective, the on-chip decoupling capacitors should be placed physically close to the current loads. The area occupied by the on-chip decoupling capacitor, however, is directly proportional to the magnitude of the capacitor. The minimum impedance between the on-chip decoupling capacitor and the current load is therefore fundamentally affected by the magnitude of the capacitor. A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. An analytic solution is shown to provide accurate distributed system. The worst case error is 0.003% as compared to SPICE. Techniques presented in this paper are applicable not only for current technologies, but also provide an efficient placement of the on-chip decoupling capacitors in future technology generations.

Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs

The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in today's systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors.

Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

With the on-going miniaturization of integrated
circuit feature size, the design of power and ground distribution
networks has become a challenging task. With technology scaling,
the requirements placed on on-chip power distribution systems have
significantly increased. The higher switching speed of a greater
number of smaller transistors produces faster and larger current
transients in the power distribution network. These conditions
place strict requirements on the on-chip power distribution network
to ensure the integrity of the on-chip power supply. To manage the
problem of high power dissipation, multiple on-chip power supply
voltages have become commonplace in nanoscale integrated circuits.
On-chip power distribution grids with multiple power supply
voltages and multiple grounds are presented in this dissertation.
The impedance characteristics of the power distribution grids with
multiple power supply voltages and multiple grounds are described.
The proposed power distribution grid structures are shown to
outperform traditional power distribution grids with multiple power
supply voltages and a single ground. Decoupling
capacitors are widely used to manage power supply noise.
Conventional approaches for placing on-chip decoupling capacitors
is shown to be ineffective in nanoscale integrated circuits. A
design methodology for placing on-chip decoupling capacitors based
on the maximum effective radii is described in this dissertation.
Techniques to estimate the minimum required on-chip decoupling
capacitance are presented. A methodology for designing decoupling
capacitors for power distribution systems with multiple power
supply voltages is also described. As the minimum feature size
continues to scale, additional on-chip decoupling capacitance will
be required to support increasing current demands. A larger on-chip
decoupling capacitance requires a greater area which cannot
conveniently be placed in proximity of the switching circuits. A
system of distributed on-chip decoupling capacitors is shown to be
a good compromise, providing the required charge drawn by the load
while satisfying existing technology constraints. The research
presented in this dissertation provides specific methodologies,
techniques, and strategies for designing robust on-chip power
distribution networks with on-chip decoupling capacitors for
application to high performance nanoscale integrated
circuits.

High Performance Power Distribution Networks with On-Chip Decoupling Capacitors for Nanoscale Integrated Circuits

In this article, acoustic noise of printed circuit board (PCB) introduced by multilayer ceramic capacitors (MLCCs) on power distribution network (PDN) is studied. The correlation of PDN power rail noise, MLCCs and PCB dynamic characteristics, and PCB acoustic noise is demonstrated on a real mobile product through electrical, vibrational, and acoustic measurements. Two measurement methodologies are proposed to identify the problematic MLCCs on the power rail. One method analyzes the board and MLCCs vibration properties with the external electrical signal applied on the power rail on a product board. Other measurement detects the problematic MLCCs based on the coherence value between the power rail signal during product operation and MLCC vibration characteristics. By replacing the identified original MLCCs with low acoustic noise ones, the PCB vibration is clearly reduced. With the MLCCs’ influence on PCB vibration studied, a measurement methodology is also proposed to analyze the PCB intrinsic vibration properties. The intrinsic modal response of PCB is applied to predict the MLCC-induced PCB vibration. The obtained modal response can also provide design guidelines for MLCC placement to reduce the level of PCB vibration.

Measurement Methodologies for Acoustic Noise Induced by Multilayer Ceramic Capacitors of Power Distribution Network in Mobile Systems

Power bus decoupling is an important part of digital printed circuit board design. Effective strategies for implementing power bus decoupling depend on the board construction as well as the demands that the circuits place on the power distribution network. This paper discusses strategies for locating and mounting decoupling capacitors in various situations as well as methods for estimating the total amount of decoupling capacitance required

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T. Hubing

Papers

Effective strategies for choosing and locating printed circuit board decoupling capacitors