International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The human visual system (HVS) is highly space-variant in sampling, coding, processing, and understanding. The spatial resolution of the HVS is highest around the point of fixation (foveation point) and decreases rapidly with increasing eccentricity. By taking advantage of this fact, it is possible to remove considerable high-frequency information redundancy from the peripheral regions and still reconstruct a perceptually good quality image. Great success has been obtained previously by a class of embedded wavelet image coding algorithms, such as the embedded zerotree wavelet (EZW) and the set partitioning in hierarchical trees (SPIHT) algorithms. Embedded wavelet coding not only provides very good compression performance, but also has the property that the bitstream can be truncated at any point and still be decoded to recreate a reasonably good quality image. In this paper, we propose an embedded foveation image coding (EFIC) algorithm, which orders the encoded bitstream to optimize foveated visual quality at arbitrary bit-rates. A foveation-based image quality metric, namely, foveated wavelet image quality index (FWQI), plays an important role in the EFIC system. We also developed a modified SPIHT algorithm to improve the coding efficiency. Experiments show that EFIC integrates foveation filtering with foveated image coding and demonstrates very good coding performance and scalability in terms of foveated image quality measurement.

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Embedded foveation image coding

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 078 LSB, an INL of 17 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 12 V supply

A 12-Bit 200-MHz CMOS ADC

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

Linearity testing of analog-to-digital converters (ADCs) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. This paper introduces the stimulus error identification and removal (SEIR) method for accurately testing ADC linearity using signal generators that may be significantly less linear than the device under test. In the SEIR approach, two imprecise nonlinear but functionally related excitations are applied to the ADC input to obtain two sets of ADC output data. The SEIR algorithm then uses the redundant information from the two sets of data to accurately identify the nonlinearity errors in the stimuli. The algorithm then removes the stimulus error from the ADC output data, allowing the ADC nonlinearity to be accurately measured. For a high resolution ADC, the total computation time of the SEIR algorithm is significantly less than the data acquisition time and therefore does not contribute to testing time. The new approach was experimentally validated on production test hardware with a commercial 16-bit successive approximation ADC. Integral nonlinearity test results that are well within the device specification of /spl plusmn/2 least significant bits were obtained by using 7-bit linear input signals. This approach provides an enabling technology for cost-effective full-code testing of high precision ADCs in production test and for potential cost-effective chip-level implementation of a built-in self-test capability.

Accurate testing of analog-to-digital converters using low linearity signals with stimulus error identification and removal

This paper is a detailed overview of the practical issues related to linearity testing of analog to digital converters The focus is on the available technology and methods for ADC linearity testing, and the goal is to demonstrate the issues and problems affecting the test capability Delta-Sigma DACs and LC filtered RF Frequency synthesizers are covered as linear sources for the ADCs Histogram based ramp and sine wave methods are covered as linearity test techniques Integral non-linearity (INL) plots from a 10-bit 20MSPS pipeline ADC are given to demonstrate the test problems and performance This work attempts to close the gap between the general theory and actual implementation problems of linearity tests for high performance ADCs

Linearity testing issues of analog to digital converters

A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of semiconductor die area. A digital-to-analog converter includes a main DAC to be calibrated, a memory, a plurality of calibration DACs, and an analog summing circuit. The main DAC receives digital input code values, and converts the respective input code values into an analog signal. A first calibration DAC receives a predetermined number of lower order bits of the respective input code values, and interpolates between a positive reference voltage and a negative reference voltage to generate linear waveforms for the PWL approximation. A second calibration DAC generates the positive reference voltage, and a third calibration DAC generates the negative reference voltage. The memory stores a plurality of PWL breakpoint code values representing respective integral non-linearity error values of the main DAC, and applies consecutive PWL breakpoint code values to the second and third calibration DACs, respectively, to generate the positive and negative reference voltages for the first calibration DAC.

All-analog calibration of sting-DAC linearity: application to high voltage processes

According to one embodiment of the present invention, a system (100) for measuring overall jitter is disclosed that includes a data converter (102) that measures a signal to generate a first measurement set (212) and a second measurement set (214), which are used to compute overall jitter. According to one embodiment of the present invention, a method for measuring overall jitter is disclosed. The data converter (102) generates the first measurement set (212) and the second measurement set (214) by measuring the signal. The overall jitter is computed using the measurement sets (212 and 214). According to one embodiment of the present invention, a system (400) for measuring internal jitter is disclosed that includes a splitter (404) that splits a signal into an input signal (406) and a clock signal (410). The data converter (102) measures the input signal (406) to generate a first data set and a second data set, which are used to compute the internal jitter of the data converter (102). According to one embodiment of the present invention, a method for measuring internal jitter is disclosed. A signal is split into an input signal (406) and a clock signal (410). The data converter (102) measures the input signal to generate the first data set (508) and the second data set (512). The internal jitter is computed using the first data set (508) and the second data set (512). The external jitter is computed from the overall and internal jitter. The signal-to-noise ratio of the data converter (102) is computed from the external jitter.

Method and system for measuring jitter

A DAC and feedback capacitor averaging (DFCA) technique used in a pipelined ADC achieves 84 dB SFDR and 74 dB SNR. Also external mismatch noise cancellation digitally improves the SNR. Excluding output drivers, the 0.6 μm double-poly BiCMOS ADC dissipates 860 mW from 3.3 V supply.

http://www.cse.psu.edu/~kxc104/class/cse577/11s/lec/lecture/PIPadc.pdf

T. Kuyel

Papers

Accurate testing of analog-to-digital converters using low linearity signals with stimulus error identification and removal

Linearity testing issues of analog to digital converters

All-analog calibration of sting-DAC linearity: application to high voltage processes

Method and system for measuring jitter

A 14 b 40 MSample/s pipelined ADC with DFCA