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Author

T. Schulz

Bio: T. Schulz is an academic researcher from Intel. The author has contributed to research in topics: System on a chip & MOSFET. The author has an hindex of 2, co-authored 2 publications receiving 119 citations.

Papers
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Journal ArticleDOI
TL;DR: In this article, a detailed physical insight on the lattice heating and heat flux in a 3D front end of the line and complex back end of line of a logic circuit network is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD.
Abstract: We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.

87 citations

Journal ArticleDOI
TL;DR: An implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance and a modification to the IF process is proposed, which helps in achieving an improved logic and analog performance for overall SoC development.
Abstract: In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a ~2× improvement in static random-access memory and digital input/ output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.

43 citations


Cited by
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Journal ArticleDOI
03 Dec 2012
TL;DR: In this paper the fundamental concept of ring amplification is introduced, and a basic operational theory is established, and the core benefits of this technique are identified.
Abstract: In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.

165 citations

Journal ArticleDOI
TL;DR: In this article, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated, and the ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL).

114 citations

Proceedings ArticleDOI
14 Apr 2013
TL;DR: In this article, the authors describe various measurements on self-heat performed on Intel's 22nm process technology and outline its reliability implications, comparing them to thermal modeling results and analytical data.
Abstract: This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

97 citations

Journal ArticleDOI
TL;DR: In this article, a detailed physical insight on the lattice heating and heat flux in a 3D front end of the line and complex back end of line of a logic circuit network is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD.
Abstract: We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.

87 citations

Journal ArticleDOI
TL;DR: A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions, which is critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability.
Abstract: A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions. 3-D self-consistent electrothermal simulations, tuned with experimentally measured electrical characteristics, were used to understand the nature of self-heating in FinFETs and calibrate the proposed model. The accuracy of the model has been demonstrated for a wide range of multifin devices by comparing it against finite element simulations. The model has been applied to carry out a detailed sensitivity analysis of self-heating with respect to various FinFET parameters and structures, which are critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability. The transient model has been used to estimate the thermal time constants of these devices and predict the sensitivity of power-to-failure to various device parameters, for both long and short pulse ESD situations. Suitable modifications to the model are also proposed for evaluating the thermal characteristics of production level FinFET (or Tri-gate FET) structures involving metal-gates, body-tied bulk FinFETs, and trench contacts.

59 citations