On robust estimation of the location parameter

비만아 부모의 돌봄 경험: q 방법론

Обнаружение транспортных средств на изображениях загородных шоссе на основе метода Single shot multibox Detector

Recent technological advances in the development of flash-memory based devices have consolidated their leadership position as the preferred storage media in the embedded systems market and opened new vistas for deployment in enterprise-scale storage systems. Unlike hard disks, flash devices are free from any mechanical moving parts, have no seek or rotational delays and consume lower power. However, the internal idiosyncrasies of flash technology make its performance highly dependent on workload characteristics. The poor performance of random writes has been a cause of major concern, which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the Flash Translation Layer (FTL), which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-based Flash Translation Layer (DFTL), which selectively caches page-level address mappings. We develop a flash simulation framework called FlashSim. Our experimental evaluation with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: (i) improved performance, (ii) reduced garbage collection overhead and (iii) better overload behavior compared to state-of-the-art FTL schemes. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared to a state-of-the-art FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%.

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DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings

Flash memory is being rapidly deployed as data storage for mobile devices such as PDAs, MP3 players, mobile phones, and digital cameras, mainly because of its low electronic power, nonvolatile storage, high performance, physical stability, and portability. One disadvantage of flash memory is that prewritten data cannot be dynamically overwritten. Before overwriting prewritten data, a time-consuming erase operation on the used blocks must precede, which significantly degrades the overall write performance of flash memory. In order to solve this “erase-before-write” problem, the flash memory controller can be integrated with a software module, called “flash translation layer (FTL).” Among many FTL schemes available, the log block buffer scheme is considered to be optimum. With this scheme, a small number of log blocks, a kind of write buffer, can improve the performance of write operations by reducing the number of erase operations. However, this scheme can suffer from low space utilization of log blocks. In this paper, we show that there is much room for performance improvement in the log buffer block scheme, and propose an enhanced log block buffer scheme, called FAST (full associative sector translation). Our FAST scheme improves the space utilization of log blocks using fully-associative sector translations for the log block sectors. We also show empirically that our FAST scheme outperforms the pure log block buffer scheme.

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A log buffer-based flash translation layer using fully-associative sector translation

A survey of Flash Translation Layer

Recently, flash memory is widely adopted in embedded applications since it has several strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristic, namely “erase before write”, it requires a software layer called FTL (Flash Translation Layer). This paper surveys the state-of-the-art FTL software for flash memory. This paper also describes problem definitions, several algorithms proposed to solve them, and related research issues. In addition, this paper provides performance results based on our implementation of each of FTL algorithms

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System software for flash memory: a survey

A method for minimizing the degradation of performance upon accessing a flash memory using a logical-physical mapping scheme, and a method for efficiently storing and managing information on logical-physical mapping in a flash memory. A method for writing data in a flash memory includes determining whether a sector is empty in a physical page having a most recently written logical page number of data to be written, the offset of the sector matching that of the data to be written; if the sector is empty, writing the data in the sector to the physical page; and if the sector is not empty, selecting an empty physical page to write the data to a sector in the selected empty physical page of which the offset matches that of the data to be written and writing a logical page number for the data to the selected empty physical page.

Address mapping method and mapping information managing method for flash memory, and flash memory using the same

A method and an apparatus for managing bad blocks generated while a flash memory is being used. A method for managing a bad block in a flash memory includes (a) allocating a used area having a plurality of used blocks and a spare area having a plurality of spare blocks in the flash memory, and providing a block map page group including a plurality of block map pages in which mapping information to map a bad block generated in either of the used area or the spare block to a spare block, (b) having mapping information of the block map page reside among the block map page groups in the memory, and (c) mapping the bad block generated during a flash operation to an unused spare block found through the mapping information, updating the mapping information, and recording the updated mapping information on the block map page.

Tae-Sun Chung

Papers

A log buffer-based flash translation layer using fully-associative sector translation

A survey of Flash Translation Layer

System software for flash memory: a survey

Address mapping method and mapping information managing method for flash memory, and flash memory using the same

Apparatus and method for managing bad blocks in a flash memory