Tae-Young Oh

Bio: Tae-Young Oh is an academic researcher from Stanford University. The author has contributed to research in topics: Gate oxide & Time-dependent gate oxide breakdown. The author has an hindex of 3, co-authored 4 publications receiving 97 citations.

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

Abstract: An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.

C-V and gate tunneling current characterization of ultra-thin gate oxide MOS (t/sub ox/=1.3-1.8 nm)

Abstract: Direct tunneling of ultra-thin gate oxides results in exponential increases in gate leakage current (Lo et al, 1997). Moreover, the loss of inversion charge due to the carrier quantization then becomes significant. Hence, more physically accurate models are urgently needed. In this paper, an equivalent circuit approach considering the gate tunneling current as well as other QM effects is presented to characterize these phenomena for gate oxide thicknesses ranging from 1.3-1.8 nm.

Hydrodynamic simulation of RF noise in deep-submicron MOSFETs

Abstract: A noise model for MOSFETs based on analytical microscopic noise sources has been developed and noise simulations based on the hydrodynamic model have been performed. The drain and gate excess noise parameters and correlation coefficient are extracted and the reasons for noise parameter dependence on the channel length are explained.

AC analysis of thin gate oxide MOS with quantum mechanical corrections

Abstract: MOS device scaling into the deep submicron regime inevitably relies on thinner gate oxide and higher substrate doping. Quantum mechanical effects must be considered in device design. This paper presents a density-gradient model which expresses the quantum mechanical effects using macroscopic approximation, and AC analysis based on it. 1D and 2D computer simulations of AC analysis show QM effects on threshold voltage and current with different gate oxide thickness and substrate doping. A simple technique to extract device parameters for circuit design is also presented.

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Abstract: The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Field effect transistors with SrTiO3 gate dielectric on Si

Abstract: SrTiO3 has been grown epitaxially by molecular beam epitaxy on Si The capacitance of this 110 A dielectric film is electrically equivalent to less than 10 A of SiO2 This structure has been used to make capacitors and metal oxide semiconductor field effect transistors The interface trap density between the SrTiO3 and the Si is 64×1010 states/cm2 eV and the inversion layer mobility is 221 and 62 cm2/V s for n- and p-channel devices, respectively The gate leakage in these devices is two orders of magnitude smaller than a similar SiO2 gate dielectric field effect transistor

Epitaxial oxide thin films on Si(001)

Abstract: Over the years, the development of epitaxial oxides on silicon has been a great technological challenge. Amorphous silicon oxide layer forms quickly at the interface when the Si surface is exposed to oxygen, making the intended oxide heteroepitaxy on Si substrate extremely difficult. Epitaxial oxides such as BaTiO3 (BTO) and SrTiO3 (STO) integrated with Si are highly desirable for future generation transistor gate dielectric and ferroelectric memory cell applications. In this article, we review the recent progress in the heteroepitaxy of oxide thin films on Si(001) substrate by using the molecular beam epitaxy technique at Motorola Labs. Structural, interfacial and electrical properties of the oxide thin films on Si have been characterized using in situ reflection high energy electron diffraction, x-ray diffraction, spectroscopic ellipsometry, atomic force microscopy, Auger electron spectroscopy, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, high-resolution transmission electron energy loss spectroscopy, capacitance–voltage and current–voltage measurement. We also present the transistor results and address the impact of the epitaxial oxide films on future generation metal-oxide-semiconductor field effect transistors.

Epitaxial perovskite thin films grown on silicon by molecular beam epitaxy

Abstract: Thin film perovskite-type oxide SrTiO3 has been grown epitaxially on Si(001) substrate by molecular beam epitaxy. Reflection high energy electron diffraction and x-ray diffraction analysis indicate high quality SrTiO3 heteroepitaxy on Si substrate with SrTiO3(001)//Si(001) and SrTiO3[010]//Si[110]. The SrTiO3 surface is atomically as smooth as the starting substrate surface, with a root mean square roughness of 1.2 A observed by atomic force microscopy. The thickness of the amorphous interfacial layer between SrTiO3 and Si has been engineered to minimize the device short channel effect. An effective oxide thickness <10 A has been obtained for a 110 A thick dielectric film. The interface state density between SrTiO3 and Si is 6.4×1010 cm−2 eV−1, and the inversion layer carrier mobilities are 221 and 62 cm2 V−1 s−1 for n- and p-channel metal–oxide–semiconductor devices with 1.2 μm effective channel length, respectively. The gate leakage in these devices is two orders of magnitude smaller than a comparable SiO2 gate dielectric metal–oxide–semiconductor field effect transistors.