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Tain-Shun Wu

Bio: Tain-Shun Wu is an academic researcher from Industrial Technology Research Institute. The author has contributed to research in topics: CMOS & Transistor. The author has an hindex of 6, co-authored 11 publications receiving 736 citations.

Papers
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Proceedings ArticleDOI
01 Dec 2008
TL;DR: In this paper, a novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology, which uses a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, and excellent memory performances such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles) have been demonstrated in the memory device.
Abstract: A novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles), and reliable data retention (10 years extrapolation at 200degC) have been demonstrated in our memory device. Moreover, the benefits of high yield, robust memory performance at high temperature (200degC), excellent scalability, and multi-level operation promise its application in the next generation nonvolatile memory.

634 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this paper, the status and challenges of the HfO X based resistive device with excellent memory properties are presented and several future challenges for the filamentary type switching device are also addressed.
Abstract: The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfO X based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.

49 citations

Patent
25 Feb 1997
TL;DR: In this paper, a MOS transistor cell is disclosed for an ESD protection circuit, output buffer, etc. The transistor cell has a regular n-sided polygonal geometry, wherein n≧8.
Abstract: A MOS transistor cell is disclosed for a multiple cell MOS transistor, such as in an ESD protection circuit, output buffer, etc. The transistor cell has a regular n-sided polygonal geometry, wherein n≧8. A drain region is provided in a substrate which occupies an area with n-sided polygonal shaped boundaries. Surrounding the drain, is a channel region which occupies an n-sided polygonal shaped area. Surrounding the channel region is a source region provided in the substrate which occupies an annular shaped area having n-sided polygonal boundaries.

41 citations

Proceedings ArticleDOI
05 May 1997
TL;DR: In this paper, a whole-chip ESD protection scheme with the ESD-connection diodes and a substrate triggering field-oxide device (STFOD) is proposed to protect mixed-mode CMOS IC's against ESD damage.
Abstract: A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an L-bits DAC chip in a 0.6-/spl mu/m CMOS process with a pin-to-pin ESD robustness of above 4 KV.

26 citations

Proceedings ArticleDOI
18 Sep 1995
TL;DR: Experimental results show that this proposed CMOS output buffer can sustain up to 4000 V (700 V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-/spl mu/m CMOS technology with LDD and polycide processes.
Abstract: There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000 V (700 V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-/spl mu/m CMOS technology with LDD and polycide processes.

20 citations


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Journal ArticleDOI
02 May 2012
TL;DR: The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide resistive switching random access memory (RRAM) are discussed, with a focus on the use of RRAM for nonvolatile memory application.
Abstract: In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

2,295 citations

Journal ArticleDOI
21 Oct 2010
TL;DR: In this paper, the authors review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the non-volatile functionalities.
Abstract: In this paper, we review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. First, we provide a brief historical overview of the research in this field. We also provide a technological overview and the epoch-making achievements, followed by an account of the current understanding of both bipolar and unipolar ReRAM operations. Finally, we summarize the challenges facing the ReRAM technology as it moves toward the beyond-2X-nm generation of nonvolatile memories and the so-called beyond complementary metal-oxide-semiconductor (CMOS) device.

824 citations

Journal ArticleDOI
26 Aug 2011-ACS Nano
TL;DR: This study shows experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems and confirms that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses plays a crucial role in determining the effectiveness of the transition.
Abstract: “Memory” is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is i...

810 citations

01 Jan 2010
TL;DR: The challenges facing the ReRAM technology as it moves toward the beyond-2X-nm generation of nonvolatile memories and the so-called beyond complementary metal-oxide-semiconductor (CMOS) device are summarized.
Abstract: In this paper, we review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. First, we provide a brief historical overview of the research in this field. We also provide a technological overview and the epoch-making achievements, followed by an account of the current understanding of both bipolar and unipolar ReRAM operations. Finally, we summarize the challenges facing the ReRAM technology as it moves toward the beyond-2X-nm generation of nonvolatile memories and the so-called beyond complementary metal-oxide-semiconductor (CMOS) device.

766 citations

Journal ArticleDOI
TL;DR: This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling, and the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms.
Abstract: With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

653 citations