Takao Arai

Bio: Takao Arai is an academic researcher from NEC. The author has contributed to research in topics: Power semiconductor device & Field-effect transistor. The author has an hindex of 1, co-authored 1 publications receiving 4 citations.

Constant voltage diode having a reduced leakage current and a high electrostatic breakdown voltage

Abstract: A semiconductor device functioning as a diode, includes an insulated-gate field effect transistor for determining a breakdown voltage, and a bipolar transistor connected to the field effect transistor for amplifying a drain current of the field effect transistor. The field effect transistor and the bipolar transistor are formed in the same semiconductor substrate.

Input/output electrostatic discharge protection circuit for an integrated circuit

Abstract: An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line V SS . The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).

Semiconductor device for supplying output voltage according to high power supply voltage

Abstract: A semiconductor device includes a p type semiconductor substrate, a first n type region formed at the semiconductor substrate, a first n channel DMOS transistor formed in the first n type region, a second n type region formed at the semiconductor substrate, a vertical type pnp bipolar transistor formed in the second n type region, and a second n channel DMOS transistor formed in the second n type region. The first n channel DMOS transistor has a drain for receiving a high power supply voltage (Vdc) and a source for supplying an output voltage (Vout). The bipolar transistor has a base connected to the gate of the first n channel DMOS transistor, an emitter connected to the source of the first n channel DMOS transistor, and a collector connected to the ground. The second n channel DMOS transistor has a drain connected to the gate of the first n channel DMOS transistor and a source connected to the ground.

Power thyristor with MOS gated turn-off and MOS-assised turn-on

Abstract: The power thyristor of this invention has a cellular emitter structure. Each cell also has a FET assisted turn-on gate integrated into the cell. A turn-on gate voltage of one polarity is applied to a FET gate element that overlies the surface of the cell and to the turn-on gate integrated into the cell. When this voltage is so applied, a channel underlying the FET gate element becomes conductive, which allows the integrated turn-on gate to provide drive to the upper base-upper emitter junction of the thyristor cell thereby turning the thyristor cell on.

Power thyristor with mos gated turn-off and turn-on

Abstract: The power thyristor (10) of the invention has a cellular emitter structure. Each cell also has a fet assisted turn-on gate integrated into the cell. A turn-on gate voltage of one polarity is applied to a fet gate element (52) that overlies the surface (26) of the cell and to the turn-on gate integrated to the cell. When this voltage is so applied, a channel underlying the fet gate element (52) becomes conductive, which allows the integrated turn-on gate to provide drive to the upper base-upper emitter junction of the thyristor cell thereby turning the thyristor cell (10) on.