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Author

Takashi Sugiyama

Bio: Takashi Sugiyama is an academic researcher. The author has contributed to research in topics: Integrator & Pulse-width modulation. The author has an hindex of 4, co-authored 4 publications receiving 77 citations.

Papers
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Journal ArticleDOI
TL;DR: The time division multiplier-type wattmeter is based on a new principle of operation as mentioned in this paper, where an operational amplifier operates as an integrator of the sum of Ez (one of the two inputs) and either +E8 or -E8, E8 being an internal standardized voltage.
Abstract: The time division multiplier-type wattmeter is based on a new principle of operation. An operational amplifier operates as an integrator of the sum of Ez (one of the two inputs) and either +E8, or -E8, E8 being an internal standardized voltage. A pulse-width modulation in the form of switch reversals is obtained which differs from balance condition by an amount proportional to Ex. Instantaneous multiplication provides a wattmeter with dc accuracy of ± 0.1 percent up to at least 10 kHz. The output voltage is ± 1 volt for a ± 1-volt input from Ex and Ey. To obtain the required flat frequency characteristics, a coupling transformer and an adjustable resistor are provided. A time constant of 6.8 X 10-9 seconds has been achieved. The voltage signal is readily provided by a precision ratiotran. Errors of ± 0.0001 percent in magnitude and 50 microradians in phase angle are reasonable.

48 citations

Patent
02 Mar 1970
TL;DR: In this article, a ratio measuring apparatus adapted to measure various parameters of impedance elements is comprised by a multiplier energized by a divisor signal, and an integrator supplied with a dividend signal and the output from the multiplier.
Abstract: Ratio measuring apparatus adapted to measure various parameters of impedance elements is comprised by a multiplier energized by a divisor signal, and an integrator supplied with a dividend signal and the output from the multiplier. A portion of the output from the integrator is fed back to the multiplier so that the integrator provides an output proportional to the ratio between the dividend signal and the divisor signal.

15 citations

Patent
03 Dec 1969
TL;DR: In this article, a periodic averaging circuit with a sampling hold circuit and a feedback circuit was proposed. But the sampling pulse was not applied to the feedback circuit, and the output of the sampling hold was fed back to the integrator.
Abstract: A periodic averaging circuit having an integrator supplied with an input signal, a sampling hold circuit supplied with the output of the integrator and a sampling pulse, and a feedback circuit for feeding the output of the sampling hold circuit back to the integrator, the sampling hold circuit holding the output of the integrator in accordance with the sampling pulse applied thereto.

9 citations

Journal ArticleDOI
TL;DR: In this paper, a pulsewidth modulation technique was used to produce a precision potentiometer with a switch, integrate, and sample-and-hold circuit, which provided digital compatibility with tape, cards, digital voltmeters etc.
Abstract: This instrument uses pulsewidth modulation techniques in which a crystal oscillator, frequency divider, and preset counter replace the resistive divider to form a precision potentiometer. The smoothing of the time-division intervals to a steady-state direct current without introducing prohibitive time constants is solved by a "sectional average" integrating circuit. This utilizes a short time-constant integrator combined with a switched unity-gain buffer amplifier in the feedback to integrator input. This switch, integrate, and sample-and-hold circuit provides output within ±0.1 percent of the eventual steady-state value in less than 400 ms after a step change and within ±0.001 percent in 600 ms. The system provides digital compatibility with tape, cards, digital voltmeters, etc. An engineering prototype has 7 decade dials covering a 0-100.0000-volt range with ±(0.1 ppm + 5?V) voltage-ratio accuracy and, ±0.05 ppm/50°C temperature coefficient and ±0.05 ppm/ 10-week long-term stability, and it is expected that this may be improved.

5 citations


Cited by
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Journal ArticleDOI
TL;DR: In this paper, the average electric power can be measured by a system that samples voltages and currents at predetermined intervals, and the sampled signals are digitized and the result is computed by numerical integration.
Abstract: Average electric power can be measured by a system that samples voltages and currents at predetermined intervals. The sampled signals are digitized and the result is computed by numerical integration. The response of the system agrees with that of a standard electrodynamic wattmeter within 0.02 percent from dc to 1 kHz, with the possible exception of zero power factor measurements. Measurements up to 5 kHz can be made with somewhat greater uncertainties.

69 citations

Journal ArticleDOI
Takaaki Yamamoto1, Y. Ohya1
TL;DR: In this paper, a new method which eliminates some disadvantages of the Epstein method has been developed for the rapid measurement of core losses and permeabilities at 50 or 60 Hz of single-sheet specimens.
Abstract: A new method which eliminates some disadvantages of the Epstein method has been developed for the rapid measurement of core losses and permeabilities at 50 or 60 Hz of single-sheet specimens. It is shown that the instrument has the following performance: 1) good correlation of the measured value with Epstein testing, 2) high stability, 3) simplicity of operation, and 4) use of a wide single-sheet specimen.

66 citations

Patent
13 May 1981
TL;DR: In this article, an improved system for generating a signal representative of the level of a material having a dielectric constant within a vessel is disclosed, which features use of a first probe for generating the signal indicative of the Dielectric constants of the material which is divided into a signal varying with the level, whereby a compensated level signal irrespective of the actual dielectrics constant is measured.
Abstract: An improved system for generating a signal representative of the level of a material having a dielectric constant within a vessel is disclosed. The system features use of a first probe for generating a signal indicative of the dielectric constant of the material which is divided into a signal varying with the level of the material whereby a compensated level signal irrespective of the actual dielectric constant is measured. In a preferred embodiment, a single integrator is used to perform the division operation whereby inaccuracies due to component variation including long-term drift are eliminated. The instrument is disclosed as functioning in a two-wire instrument system having low power requirements, permitting use of conventional signal limits. Means for calibrating the instrument in a fail-safe manner such that the operator is assured of proper calibration are disclosed, as is means whereby bridge circuits used to measure in the capacitance measurements supplied to the division circuit are both supplied by a single oscillator means, again increasing reliability and accuracy of the system.

64 citations

Patent
28 Oct 1987
TL;DR: In this article, a voltage-to-duty-cycle modulator, a non-galvanic isolation barrier, and a demodulator convert a duty-cycle-modulated signal transmitted across the isolation barrier to an analog voltage replica of the analog input voltage.
Abstract: An isolation amplifier includes a voltage-to-duty-cycle modulator, a non-galvanic isolation barrier, and a demodulator converting a duty-cycle-modulated signal transmitted across the isolation barrier to an analog voltage replica of the analog input voltage. The modulator circuit includes a first current switching means which produces a first current that is switched between positive and negative values in response to an output from a comparator that can be referenced to a noise-synchronized signal. The first current is summed with an input current and the difference is integrated and input to the comparator, the output of which produces the duty-cycle-modulated signal. The demodulator includes a second current switching circuit for producing a second current that is switched between positive and negative levels in response to the duty-cycle-modulated signal received across the isolation barrier and includes circuitry for algebraically summing the input current with the second current and integrating the result to produce the analog output voltage. The modulator circuit and demodulator circuits are fabricated on a single semiconductor area to produce the close matching between components of the first and second current switching circuits. The area is cut in half to produce two chips, which are connected to two isolation barrier capacitors. In the demodulator, a sample and hold circuit synchronized with the duty-cycle-modulated signal transmitted across the isolation barrier samples the output of the integrator.

61 citations

Patent
17 Dec 1984
TL;DR: In this article, an amplifier circuit for an IR detector array formed on a large-scale integrated structure is presented, which includes an amplifier stage capacitively coupled to an external biasing source and another switching FET 24 to reset the amplifier stage after an integration period.
Abstract: An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal. In still another embodiment the output stage 128 includes a second capacitor 132 of smaller capacitance onto which a charge of the first capacitor 130 proportional to the output of the amplifier stage is placed for subsequent sampling.

47 citations