A technique for hierarchical display of control and dataflow graphs allowing a user to view hierarchically filtered control and dataflow information related to a design. The technique employs information inherent in the design description and information derived from design synthesis to identify "modules" of the design and design hierarchy. The user can specify a level of detail to be displayed for any design element or group of design elements. Any CDFG (control and dataflow graph) object can be "annotated" with a visual attribute or with text to indicate information about the design elements represented by the object. For example, block size, interior color, border color, line thickness, line style, etc., can be used to convey quantitative or qualitative information about a CDFG object. Examples of information which can be used to "annotate" objects include power dissipation, propagation delay, the number of HDL statement represented, circuit area, number of logic gates, etc. The user is able to expand and/or compress CDFG blocks either "in-place" on a higher level CDFG display or to be displayed in isolation. Simulation-related data can also be used to annotate the CDFG. By viewing CDFG's (particularly annotated CDFG's) for a variety of trial designs, a problem-solving user can gain quick insight into the effects and effectiveness of various design choices.

Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information

A method for constrained material requirements planning, optimal resource allocation, and production planning provides for an optimization of a manufacturing process by designating the amounts of various manufactured products to be produced, which products include both end products as well as subassemblies to be employed in the manufacture of one or more of the end products. In order to accomplish the optimization, the method employs an objective function such as the maximization of income in a situation wherein there are limitations on the inventory of raw materials and tools to be employed in the manufacturing process. Data describing elemental steps in the manufacturing process for the production of each end product, as well as the quantity or demand for each end product which is to be supplied, are presented as a set of linear mathematical relationships in matrix form to be inserted in a computer which determines the optimum number of each end product in accordance with an LP optimization algorithm. The matrix contains bill of material data, and various constraints such as a constraint on the sum of products shipped and used as subassemblies, and constraints based on inventory, on available time for use of resources such as tools, and on inventory left over from an early production run for a later run.

Optimization of manufacturing resource planning

A hardware device architecture is described that improves security and flexibility in access to hardware device settings. A device management proxy service is digitally signed and granted access to device settings. Applications are then digitally provisioned by the proxy service and only validated signed requests from applications are permitted to change hardware device settings. Further granularity over hardware device settings is achieved through user accounts and groups established by the applications.

Device management proxy for secure devices

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

Long Instruction Word Controlling Plural Independent Processor Operations

An operating system for a non-uniform memory access (NUMA) multiprocessor system that utilizes a software abstraction of the NUMA system hardware representing a hierarchical tree structure to maintain the most efficient level of affinity and to maintain balanced processor and memory loads. The hierarchical tree structure includes leaf nodes representing the job processors, a root node representing at least one system resource shared by all the job processors, and a plurality of intermediate level nodes representing resources shared by different combinations of the job processors. The operating system includes a medium term scheduler for monitoring the progress of active thread groups distributed throughout the system and for assisting languishing thread groups, and a plurality of dispatchers each associated with one of the job processors for monitoring the status of the associated job processor and for obtaining thread groups for the associated job processor to execute. The operating system further includes a memory manager for allocating virtual and physical memory using a plurality of memory pools and frame treasuries.

Operating system for a non-uniform memory access multiprocessor system

A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.

Design of high speed MOS multiplier and divider using redundant binary representation

To achieve an LSI automated design satisfying a required function and a required performance with the reuse of existing design data, there are disposed: library element memory means for storing, in the form of elements, existing design data (circuit data) together with design procedures (conversion information) thereof; element arrangement entering means for entering an element arrangement for achieving the desired function; library element specializing means for determining the functions of general-purpose elements; element synthesizing means for synthesizing an element having one function in which the functions of the elements are combined with one another; design data memory means for storing a variety of data; conversion instruction entering means for entering a design target level; conversion method selecting means for selecting a method of converting the elements to the target level, based on information relating to the design procedure of each of the elements; and design data converting means for executing the conversion of the elements according to the selected method.

LSI automated design system

An apparatus and method for translating a function description of a circuit presented in hardware description language includes parsing the function description of the circuit to generate a parse tree. The structure of the parse tree is deformed to optimize the test level redundancy of the function description to thereby generate a deformed parse tree. The deformed parse tree is then translated into function blocks representing a hardware configuration of the circuit set forth by the function description.

Logic design system for creating circuit configuration by generating parse tree from hardware description language and optimizing text level redundancy thereof

An improved LSI design automation system is disclosed which is implemented by making optimum reuse of previously applied design method information. This LSI design automation system includes the following: an input unit, a circuit component storage unit, a circuit component selection unit, a design method decision unit, a design process unit, and a component entry unit. The input unit receives LSI function and performance information as a requirements specification and LSI component configuration information. The circuit component storage unit collectively stores a circuit data item, design method information items, and performance information items, as a circuit component. The circuit component selection unit selects a circuit component from the circuit component storage unit for implementation of a desired circuit. The design method decision unit selects an optimum design method information item from the design method information items held by each circuit component. The design process unit generates, modifies, and evaluates a circuit. The component entry unit enters a result of the modification made during the design and a newly generated circuit component into the circuit component storage unit.

LSI design automation system

There are provided a communications system between a vehicle, a home and a center, a vehicle information communicating apparatus and an indoor information processing apparatus which imposes no limitation on communicating time enables bulk communication. The communications system comprises an on-board server and DSRC on-board equipment which are installed on the vehicle 10 and includes a DSRC base station 23 residing outside the vehicle which can communicate with the DSRC on-board equipment and a PC or a home server 22 residing indoors which is connected to the DSRC base station 23, the communication system having a detection means installed on the vehicle and/or an indoor detection means for detecting the state of the vehicle 10 and a communication activating means for activating the communication of information between the on-board server and the PC or the home server 22 using the detection result of either or both of the detection means.

Tamotsu Nishiyama

Papers

Design of high speed MOS multiplier and divider using redundant binary representation

LSI automated design system

Logic design system for creating circuit configuration by generating parse tree from hardware description language and optimizing text level redundancy thereof

LSI design automation system

Communication system, vehicle information communicating apparatus, and indoor information processing apparatus