Tang Ju

Bio: Tang Ju is an academic researcher from Peking University. The author has contributed to research in topics: CMOS & Readout integrated circuit. The author has an hindex of 5, co-authored 7 publications receiving 29 citations.

Low Power Design of Column Readout Stage for 320x288 Snapshot Infrared ROIC

Abstract: A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 674mw, which reduced more than 85% In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 05μm DPDM n-well CMOS process

Design of high performance CMOS linear readout integrated circuit

Abstract: This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.

The study of dual-window random addressable ROIC

Abstract: A novel dual-window readout structure is presented in this paper The ROIC with this structure can work in two modes: normal mode and windowing mode The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode Furthermore, the positions and sizes of these sub-arrays can be specified by users This feature allows image system to trace two fast moving objects without using two ROICs An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 05/spl mu/m DPTM n-well CMOS process

A precise compensated bandgap reference without resistors

Abstract: This paper presents a precise compensated bandgap reference without resistors This bandgap reference uses an improved voltage-transfer unit instead of resistors A current proportional to T/sup /spl alpha// (/spl alpha/ is a constant) is produced to compensate for the higher order of the V/sub EB/ This bandgap reference is based on 05/spl mu/m n-well CMOS technology The supply voltage is 5V, working from -10/spl deg/C to 90/spl deg/C, the effective temperature coefficient of the output voltage is only 7 ppm//spl deg/C, and the maximum power dissipation is 076mW

A novel low-power readout structure for TDI ROIC

Abstract: A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.

Time-Delay-Integration Architectures in CMOS Image Sensors

Abstract: Difficulty and challenges of implementing time-delay-integration (TDI) functionality in a CMOS technology are studied: synchronization of the samples forming a TDI pixel, adder matrix outside the array, and addition noise. Existing and new TDI sensor architecture concepts with snapshot shutter, rolling shutter, or orthogonal readout are presented. An optimization method is then introduced to inject modulation transfer function and quantum efficiency specification in the architecture definition. Moderate spatial and temporal oversamplings are combined to achieve near charge-coupled device (CCD) class performances, resulting in an acceptable design complexity. Finally, CCD and CMOS dynamic range and signal-to-noise ratio are conceptually compared.

Curvature compensated bandgap voltage reference

Abstract: Embodiments of the present invention include systems and methods for generating a curvature compensated bandgap voltage reference. In an embodiment, a curvature compensated bandgap reference voltage is achieved by injecting a temperature dependent current at different points in the bandgap reference voltage circuit. In an embodiment, the temperature dependent current is injected in the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) current generation block of the bandgap circuit. Alternatively, or additionally, the temperature dependent current is injected at the output stage of the bandgap circuit. In an embodiment, the temperature dependent current is a linear piecewise continuous function of temperature. In another embodiment, the temperature dependent current has opposite dependence on temperature to that of the bandgap voltage reference before curvature compensation.

Design of a ROIC for Scanning Type HgCdTe LWIR Focal Plane Arrays

Abstract: Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.

A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage

Abstract: A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.

Automated conversion of synchronous to asynchronous circuit design representations

Abstract: Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions.