Tanmay Biswas

Bio: Tanmay Biswas is an academic researcher from Information Technology University. The author has contributed to research in topics: Speech enhancement & Field-programmable gate array. The author has an hindex of 2, co-authored 8 publications receiving 16 citations. Previous affiliations of Tanmay Biswas include University of Calcutta.

A novel AES-256 implementation on FPGA using co-processor based architecture

Abstract: Efficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and requires less resource as compared to the software implementation, and hence ideally suited for target specific embedded systems. Though, there exist quite a few research works that propose hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers, still there lies the need of better hardware design in terms of larger key values, higher throughput and less resource utilization.

Audio de-noising by spectral subtraction technique implemented on reconfigurable hardware.

Abstract: This paper proposes an efficient hardware architecture for the spectral subtraction algorithm applied to speech enhancement. Spectral subtraction algorithm is widely used in audio de-noising applications. The proposed architecture uses a novel approach to estimate environmental noise from speech adaptively. After estimating the noise from the input speech the noise samples are subtracted, making it noise free. In this design we have two principal blocks, the noise estimation-subtraction block and the phase block, which are executed concurrently exploiting the parallel logic blocks of field programmable gate array (FPGA). We have implemented our design on Spartan6 LX45 FPGA, which also meets the high speed requirements. Resource utilization and delay information for the different blocks in our design are presented. Our proposed hardware implementation shows a better SNR value compared to the original software implementation. To the best of our knowledge, this work is the first of its kind of implementation in regards to FPGA based hardware design for adaptive noise filtering in speech.

FPGA based dual microphone speech enhancement

Abstract: This paper proposes an efficient reconfigurable hardware design of dual microphone speech enhancement technique using sound source localization and multi band spectral subtraction methods with elimination of background noise. Firstly, we have used a time delay of arrival algorithm using phase transform (PHAT) to achieve the time difference between the microphone signals. PHAT based filter can reach high SNR gains, which makes it very suitable for localizing the sound source in a microphone array system. After adjustment of the delay between the signals, multi band spectral subtraction technique enhances the signal from the background noise environment in each of the frequency bands. Our design has been implemented in Spartan6 Lx45 FPGA and we have presented the implementation results in terms of subjective and objective evaluations. We have also compared the angular separation between the microphones to the resultant angle between the microphones and observed that proposed design provides very sharp accuracy in every corresponding angle. The objective and subjective evaluation established that our design provides better throughput compared to the existing state of the art research works. The evaluation infers that our proposed hardware induce feasibility for hand-held devices in background noisy environment.

Dual Microphone Sound Source Localization Using Reconfigurable Hardware

Abstract: This paper proposes an efficient reconfigurable hardware design of sound source localization system using one microphone pair We have used time delay of arrival (TDOA) algorithm using phase transform (PHAT) to achieve time difference between the microphone signals Phased transform (PHAT) based filter can reach high SNR gains, which makes it very suitable for localizing the sound source in a microphone array system Our design has implemented on Spartan6 Lx45 FPGA and presented the implementation results in terms of accuracy and speech quality We compare the original angle between the microphones to the resultant angle between the microphones and observed that proposed design provides very sharp accuracy in every corresponding angle We also compare the speech quality of proposed design signal with normal delayed signal The evaluation infers that our proposed hardware induce feasible for hand-held devices

A Novel Reconfigurable Hardware Design for Speech Enhancement Based on Multi-Band Spectral Subtraction Involving Magnitude and Phase Components

Abstract: This paper proposes an efficient reconfigurable hardware design for speech enhancement based on multi band spectral subtraction algorithm and involving both magnitude and phase components. Our proposed design is novel as it estimates environmental noise from speech adaptively utilizing both magnitude and phase components of the speech spectrum. We performed multi-band spectrum subtraction by dividing the noisy speech spectrum into different non-uniform frequency bands having varying signal to noise ratio (SNR) and subtracting the estimated noise from each of these frequency bands. This results to the elimination of noise from both high SNR and low SNR signal components for all the frequency bands. We have coined our proposed speech enhancement technique as Multi Band Magnitude Phase Spectral Subtraction (MBMPSS). The magnitude and phase operations are executed concurrently exploiting the parallel logic blocks of Field Programmable Gate Array (FPGA), thus increasing the throughput of the system to a great extent. We have implemented our design on Spartan6 Lx45 FPGA and presented the implementation result in terms of resource utilization and delay information for the different blocks of our design. To the best of our best knowledge, this is a new type of hardware design for speech enhancement application and also a first of its kind implementation on reconfigurable hardware. We have used benchmark audio data for the evaluation of the proposed hardware and the experimental results show that our hardware shows a better SNR value compared to the existing state of the art research works.

Advanced Encryption Standard (AES).

Abstract: Im Jahre 1977 wurde der „Data Encryption Algorithm“ (DEA) vom „National Bureau of Standards“ (NBS, später „National Institute of Standards and Technology“ – NIST) zum amerikanischen Verschlüsselungsstandard für Bundesbehörden erklärt [NBS_77]. 1981 folgte die Verabschiedung der DEA-Spezifikation als ANSI-Standard „DES“ [ANSI_81]. Die Empfehlung des DES als StandardVerschlüsselungsverfahren wurde auf fünf Jahre befristet und 1983, 1988 und 1993 um jeweils weitere fünf Jahre verlängert. Derzeit liegt eine Neufassung des NISTStandards vor [NIST_99], in dem der DES für weitere fünf Jahre übergangsweise zugelassen sein soll, aber die Verwendung von Triple-DES empfohlen wird: eine dreifache Anwendung des DES mit drei verschiedenen Schlüsseln (effektive Schlüssellänge: 168 bit) [NIST_99]. Der DES basiert auf einer von Horst Feistel bei IBM entwickelten Blockchiffre („Lucipher“) mit einer Schlüssellänge von 128 bit. Da die amerikanische „National Security Agency“ (NSA) dafür gesorgt hatte, daß der DES eine Schlüssellänge von lediglich 64 bit besitzt, von denen nur 56 bit relevant sind, und spezielle Substitutionsboxen (den „kryptographischen Kern“ des Verfahrens) erhielt, deren Konstruktionskriterien von der NSA nicht veröffentlicht wurden, war das Verfahren von Beginn an umstritten. Kritiker nahmen an, daß es eine geheime „Trapdoor“ in dem Verfahren gäbe, die der NSA eine OnlineEntschlüsselung auch ohne Kenntnis des Schlüssels erlauben würde. Zwar ließ sich dieser Verdacht nicht erhärten, aber sowohl die Zunahme von Rechenleistung als auch die Parallelisierung von Suchalgorithmen machen heute eine Schlüssellänge von 56 bit zum Sicherheitsrisiko. Zuletzt konnte 1998 mit einer von der „Electronic Frontier Foundation“ (EFF) entwickelten Spezialmaschine mit 1.800 parallel arbeitenden, eigens entwickelten Krypto-Prozessoren ein DES-Schlüssel in einer Rekordzeit von 2,5 Tagen gefunden werden. Um einen Nachfolger für den DES zu finden, kündigte das NIST am 2. Januar 1997 die Suche nach einem „Advanced Encryption Standard“ (AES) an. Ziel dieser Initiative ist, in enger Kooperation mit Forschung und Industrie ein symmetrisches Verschlüsselungsverfahren zu finden, das geeignet ist, bis weit ins 21. Jahrhundert hinein amerikanische Behördendaten wirkungsvoll zu verschlüsseln. Dazu wurde am 12. September 1997 ein offizieller „Call for Algorithm“ ausgeschrieben. An die vorzuschlagenden symmetrischen Verschlüsselungsalgorithmen wurden die folgenden Anforderungen gestellt: nicht-klassifiziert und veröffentlicht, weltweit lizenzfrei verfügbar, effizient implementierbar in Hardund Software, Blockchiffren mit einer Blocklänge von 128 bit sowie Schlüssellängen von 128, 192 und 256 bit unterstützt. Auf der ersten „AES Candidate Conference“ (AES1) veröffentlichte das NIST am 20. August 1998 eine Liste von 15 vorgeschlagenen Algorithmen und forderte die Fachöffentlichkeit zu deren Analyse auf. Die Ergebnisse wurden auf der zweiten „AES Candidate Conference“ (22.-23. März 1999 in Rom, AES2) vorgestellt und unter internationalen Kryptologen diskutiert. Die Kommentierungsphase endete am 15. April 1999. Auf der Basis der eingegangenen Kommentare und Analysen wählte das NIST fünf Kandidaten aus, die es am 9. August 1999 öffentlich bekanntmachte: MARS (IBM) RC6 (RSA Lab.) Rijndael (Daemen, Rijmen) Serpent (Anderson, Biham, Knudsen) Twofish (Schneier, Kelsey, Whiting, Wagner, Hall, Ferguson).

FPGA-Based Architectures for Acoustic Beamforming with Microphone Arrays: Trends, Challenges and Research Opportunities

Abstract: Over the past decades, many systems composed of arrays of microphones have been developed to satisfy the quality demanded by acoustic applications. Such microphone arrays are sound acquisition systems composed of multiple microphones used to sample the sound field with spatial diversity. The relatively recent adoption of Field-Programmable Gate Arrays (FPGAs) to manage the audio data samples and to perform the signal processing operations such as filtering or beamforming has lead to customizable architectures able to satisfy the most demanding computational, power or performance acoustic applications. The presented work provides an overview of the current FPGA-based architectures and how FPGAs are exploited for different acoustic applications. Current trends on the use of this technology, pending challenges and open research opportunities on the use of FPGAs for acoustic applications using microphone arrays are presented and discussed.

An Efficient Porcine Acoustic Signal Denoising Technique Based on EEMD-ICA-WTD

Abstract: Automatic monitoring of group-housed pigs in real time through porcine acoustic signals has played a crucial role in automated farming. In the process of data collection and transmission, acoustic signals are generally interfered with noise. In this paper, an effective porcine acoustic signal denoising technique based on ensemble empirical mode decomposition (EEMD), independent component analysis (ICA), and wavelet threshold denoising (WTD) is proposed. Firstly, the porcine acoustic signal is decomposed into intrinsic mode functions (IMFs) by EEMD. In addition, permutation entropy (PE) is adopted to distinguish noise-dominant IMFs from the IMFs. Secondly, ICA is employed to extract the independent components (ICs) of the noise-dominant IMFs. The correlation coefficients of ICs and the first IMF are calculated to recognize noise ICs. The noise ICs will be removed. Then, WTD is applied to the other ICs. Finally, the porcine acoustic signal is reconstructed by the processed components. Experimental results show that the proposed method can effectively improve the denoising performance of porcine acoustic signal.

Audio Denoising Based on Short Time Fourier Transform

Abstract: This paper presents a novel audio de-noising scheme in a given speech signal. The recovery of original from the communication channel without any noise is a difficult task. Many de-noising techniques have been proposed for the removal of noises from a digital signal. In this paper, an audio de-noising technique based on Short Time Fourier Transform (STFT) is implemented. The proposed architecture uses a novel approach to estimate environmental noise from speech adaptively. Here original speech signals are given as input signal. Using AWGN, noises are added to the signal. Then noised signals are de-noised using STFT techniques. Finally Signal to Noise Ratio (SNR), Peak Signal to Noise Ratio (PSNR) values for noised and de-noised signals are obtained.

Secure Distributed Storage and Retrieval.

Abstract: In his well-known Information Dispersal Algorithm paper, Rabin showed a way to distribute information in n pieces among n servers in such a way that recovery of the information is possible in the presence of up to t inactive servers. An enhanced mechanism to enable construction in the presence of malicious faults, which can intentionally modify their pieces of the information, was later presented by Krawczyk. Yet, these methods assume that the malicious faults occur only at reconstruction time. In this paper we address the more general problem of secure storage and retrieval of information (SSRI), and guarantee that also the process of storing the information is correct even when some of the servers fail. Our protocols achieve this while maintaining the (asymptotical) space optimality of the above methods. We also consider SSRI with the added requirement of confidentiality, by which no party except for the rightful owner of the information is able to learn anything about it. This is achieved through novel applications of cryptographic techniques, such as the distributed generation of receipts, distributed key management via threshold cryptography, and “blinding”. An interesting byproduct of our scheme is the construction of a secret sharing scheme with shorter shares size in the amortized sense. An immediate practical application of our work is a system for the secure deposit of sensitive data. We also extend SSRI to a “proactive” setting, where an adversary may corrupt all the servers during the lifetime of the system, but only a fraction during any given time interval.