The machine learning community currently has no standardized process for documenting datasets, which can lead to severe consequences in high-stakes domains. To address this gap, we propose datasheets for datasets. In the electronics industry, every component, no matter how simple or complex, is accompanied with a datasheet that describes its operating characteristics, test results, recommended uses, and other information. By analogy, we propose that every dataset be accompanied with a datasheet that documents its motivation, composition, collection process, recommended uses, and so on. Datasheets for datasets will facilitate better communication between dataset creators and dataset consumers, and encourage the machine learning community to prioritize transparency and accountability.

Datasheets for Datasets

Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new byte-addressable, persistent memory technologies such as phase change memory (PCM) offer fast, fine-grained access to persistent storage.In this paper, we present a file system and a hardware architecture that are designed around the properties of persistent, byteaddressable memory. Our file system, BPFS, uses a new technique called short-circuit shadow paging to provide atomic, fine-grained updates to persistent storage. As a result, BPFS provides strong reliability guarantees and offers better performance than traditional file systems, even when both are run on top of byte-addressable, persistent memory. Our hardware architecture enforces atomicity and ordering guarantees required by BPFS while still providing the performance benefits of the L1 and L2 caches.Since these memory technologies are not yet widely available, we evaluate BPFS on DRAM against NTFS on both a RAM disk and a traditional disk. Then, we use microarchitectural simulations to estimate the performance of BPFS on PCM. Despite providing strong safety and consistency guarantees, BPFS on DRAM is typically twice as fast as NTFS on a RAM disk and 4-10 times faster than NTFS on disk. We also show that BPFS on PCM should be significantly faster than a traditional disk-based file system.

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Better I/O through byte-addressable, persistent memory

Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to today's billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.

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The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

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Power distribution networks for system-on-package: status and challenges

Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.

Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation

Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

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Power distribution system design methodology and capacitor selection for modern CMOS technology

A SPICE model for power plane simulation has been developed. It is based on the geometries and materials of the power planes and uses a unit cell composed of RLC elements, transmission line elements or the HSPICE W-element. Simulated resonances in the frequency domain and delays in the time domain are consistent with results calculated from physical dimensions. SPICE model simulations compare well with hardware measurements in both the frequency and time domains. The role of dielectric thickness, dielectric constant and parallel pairs of power planes is demonstrated through simulation. The spreading inductance of power planes is defined, discussed and measured. Power plane performance in terms of impedance, resonances, damping and spreading inductance is optimized by the use of a thin dielectric layer between conductive planes.

Power plane SPICE models and simulated performance for materials and geometries

A method for determining the desired decoupling components for stabilizing the electrical impedance in the power distribution system of an electrical interconnecting apparatus, including a method for measuring the ESR for an electrical device, a method for determining a number of desired decoupling components for a power distribution system, and a method for placing the desired decoupling components in the power distribution system. The method creates a model of the power distribution system based upon an MxN grid for both the power plane and the ground plane. The model receives input from a user and from a database of various characteristics for a plurality of decoupling components. The method determines a target impedance over a desired frequency range. The method selects decoupling components. The method determines a number for each of the decoupling components chosen. The method places current sources in the model at spatial locations corresponding to physical locations of active components. The method optionally also places a power supply in the model. The method selects specific locations in the model to calculate transfer impedance values as a function of frequency. The method effectuates the model to determine the transfer impedance values as the function of frequency at the specific locations previously chosen. The method then compares the transfer impedance values as the function of frequency at the specific locations to the target impedance for the power distribution system. The method determines a bill of goods for the power distribution system based upon the results of effectuating the model.

Method for determining the desired decoupling components for power distribution systems

A SPICE model for power plane simulation has been developed. It is based on the geometries and materials of the power planes and uses a unit cell composed of RLC elements, transmission line elements or the W-element. Important frequency and time domain properties are demonstrated through simulation, and model to hardware correlation is established in both domains.

Tanmoy Roy

Papers

Power distribution system design methodology and capacitor selection for modern CMOS technology

Power plane SPICE models and simulated performance for materials and geometries

Method for determining the desired decoupling components for power distribution systems

Power plane SPICE models for frequency and time domains

Power distribution system design methodology and capacitor selection for modern CMOS technology