Tapas Kumar Bayen

Bio: Tapas Kumar Bayen is an academic researcher. The author has contributed to research in topics: Policy-based routing & Static routing. The author has an hindex of 1, co-authored 1 publications receiving 1 citations.

A Review on Channel Routing On VLSI Physical Design

Abstract: We know that channel routing is very important problem in VLSI physical design. The main objective of a channel routing algorithm is the reduction of the area of a IC chip. In this paper, we just do a survey on some impotent multi-layer routing algorithms. Here we analyze The Efficient Routing algorithm and resolve horizontal constraints and minimize the net wirelength in a particular model of channel routing using MCC1 and MCC2 algorithms. Next, we analyze an algorithm for Multi channel Routing MulCh and its differences from Chameleon which s another multi channel routing in the two-layer VH and three-layer HVH routing models.

Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

Abstract: Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.