Among the emerging technologies Field-Coupled devices like Quantum dot Cellular Automata are one of the most interesting. Of all the practical implementations of this principle NanoMagnet Logic shows many important features, such like a very low power consumption and the feasibility with up-to-date technology. However its working principle, based on the interaction among neighbor cells, is quite different from CMOS circuits. Dedicated design and simulation tools for this technology are necessary to further study this technology, but at the moment there are no such tools available in the scientific scenario.

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ToPoliNano: NanoMagnet Logic Circuits Design and Simulation

Green technology is a new research area in electronics, which meets the needs of society and explores the ability of VLSI circuits and embedded systems to positively impact the environment In VLSI physical design automation, channel routing is a fundamental problem but reducing the total wire length for interconnecting the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed Reducing the total wire length for interconnection not only minimizes the cost of the physical wire segments required, but also reduces the amount of occupied area for interconnection, signal propagation delays, electrical hazards, power consumption, heat generation, and over all the parasitics present in a circuit Thus it has a direct impact on daily life and environment Channel routing problem for wire length minimization is an NP-hard problem Hence as a part of developing an alternative, we modify the existing graph theoretic framework Track_Assignment_Heuristic (TAH) to reduce the total (vertical) wire length In this paper we propose an efficient polynomial time graph based parallel algorithm to reduce the total wire length without radically increasing of required area for interconnection in the reserved two-layer no-dogleg Manhattan channel routing model The performance and efficiency of our algorithm is highly encouraging for different well-known benchmarks channels

An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits

To trigger events for application-specific data transfer among registers in a multimillion-gate system-on-chip (SoC), various kinds of clock signals, selectively driven by different frequency-dependent sources and/or dividers (DIVs), are usually centralized in one or more clock generation modules, where clock gating cells (CGCs), multiplexers (MUXes) and DIVs are used to create the clocks required by different functional operations in an SoC. These modules will introduce uncommon and longer timing paths for clock propagations and further make the clock tree synthesis (CTS) process become more challenging due to the on-chip-variation (OCV) effects. In addition, high volume of switching activities in the increased number of clock logic cells will consume more power. In this article, a novel design platform, merging and replacing of multiple multiplexers and dividers (MRMMD), is developed to intelligently identify those suspicious clock architectures and resynthesize them into a power-and-area effective and less complicated clock structure. Using our resynthesis platform, not only the number of clock-related timing paths and their corresponding logic levels can be reduced, but also the corresponding analysis and implementations of clock skew minimizations during CTS become much easier. The experimental results implemented in TSMC 55- and 28-nm process nodes on optimizing some industrial clock architectures showed that significant reductions of area, power, latency, skew and clock path, logic level, OCV impact, total wire length, and implementation runtime are achieved using our MRMMD platform.

A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees

In graph theory, generation of random graphs finds a wide range of applications in different scheduling problems, approximation algorithms, problems involving modeling and simulation, different database applications, and obviously to test the performance of any algorithm. The algorithm, which has been devised in this paper, is mainly for the purpose of providing test bed for checking performance of other algorithms. It generates different non-isomorphic graph instances of a given order and having unique number of edges. The number of such instances possible for a graph of given order has also been subsequently formulated. Different such graph instances of different orders, generated in a uniform computing environment, and the computing time required for such generations have also been included in this paper. The simplicity and efficiency of the algorithm, subsequently proved in the paper, give us a new insight in the area of random graph generation and have called for further research scope in the domain.

Generation of Simple, Connected, Non-isomorphic Random Graphs

A nonlinear crosstalk minimization algorithm that simultaneously considers SPM, XPM and FWM is presented and experimentally assessed. For a PON worst-case scenario a 1 dB power gain is obtained for a BER of 10-9.

Experimental demonstration of a nonlinear effects crosstalk minimization algorithm

Minimization of total (vertical) wire length is one of the most important problems in laying out blocks in VLSI physical design. Minimization of wire length not only reduces the cost of physical wiring required, but also reduces the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg, two-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as low total (vertical) wire length as possible. In this paper we develop an efficient heuristic algorithm for appreciably reducing the total wire length in the reserved two-layer no-dogleg Manhattan channel routing model. Experimental results obtained are greatly encouraging.

A graph based algorithm to minimize total wire length in VLSI channel routing

Crosstalk minimization is one of the most important high performance aspects in interconnecting VLSI circuits. With advancement of fabrication technology, devices and interconnecting wires are placed in closer proximity and circuits operate at higher frequencies. This results in crosstalk between wire segments. Crosstalk minimization problem for the reserved two-layer Manhattan channel routing is NP-hard, even if the channel instances are free from any vertical constraint (simplest channel instances). In this paper we have developed heuristic algorithms for computing reduced crosstalk two-layer channel routing solutions for simplest as well as general channel instances. In general, the results obtained are highly encouraging.

Algorithms for high performance two-layer channel routing

With advancements in VLSI fabrication technology, interconnecting wires are being placed in closer proximity while circuits are starting to operate at higher frequencies. Thus, reduction in crosstalk between interconnects becomes an important consideration for VLSI physical design. In this paper, we have reviewed the effects and impact that crosstalk has on the performance and reliability of VLSI circuits and systems. We have also presented a concise but informative review on the various methods that researchers worldwide are implementing for a priori crosstalk avoidance or a posteriori crosstalk minimization in VLSI systems from the point of view of fabrication over the past few decades.

A Review on Crosstalk Avoidance and Minimization in VLSI Systems

The main objective of VLSI channel routing problem is to compute a feasible reduced area routing solution which reduces the height of the channel. A channel is a rectangular routing region with two open ends (left and right) and two sets of fixed terminals (top terminals and bottom terminals) are placed in the upper and lower sides of the channel. A net is a set of terminals that need to be electrically connected (usually using rectilinear wiring). Routing is a process to interconnect all nets within the channel considering all constraints (horizontal and vertical constraints) of that channel. The terminals along the left and right ends of the channel are not fixed, known as floating terminals. Generally, channel routing problem for area minimization is NP-complete. So developing a heuristic algorithm is really interesting. In this paper, we consider a general channel routing problem for channel instances with fixed and floating terminals, and develop an efficient graph based heuristic algorithm for reducing area in the reserved two-layer Manhattan channel routing model.

Yet an efficient algorithm for computing reduced area VLSI channel routing solutions with floating terminals

In this paper we develop algorithms for generating random channel specifications of channel routing problem in VLSI design. A channel is a rectangular routing region containing two sets of fixed terminals on two of its opposite sides and the other two opposite sides (of the rectangle) are open ends, may or may not contain any terminal of a net but the terminal position is not fixed before a routing solution is computed. Most of the problems in two-, three-, and multi-layer channel routing are beyond polynomial time computable. Hence for each of these problems it is unlikely to design a polynomial time deterministic algorithm. Developing heuristic algorithm might be a probable way out that hopefully provides good solutions for most of the instances occur in practice. Novelty of a heuristic algorithm is judged better if it works for a variety of large number of randomly generated instances of the problem. In fact, convergence of results of a heuristic algorithm is well established when the algorithm of a problem is executed for a huge number of randomly generated similar instances and the final result is computed making an average on all of them.

Tarak N. Mandal

Papers

A graph based algorithm to minimize total wire length in VLSI channel routing

Algorithms for high performance two-layer channel routing

A Review on Crosstalk Avoidance and Minimization in VLSI Systems

Yet an efficient algorithm for computing reduced area VLSI channel routing solutions with floating terminals

Generation of random channel specifications for channel routing problem