T
Teerath Das
Researcher at South Asian University
Publications - 41
Citations - 453
Teerath Das is an academic researcher from South Asian University. The author has contributed to research in topics: Field-programmable gate array & Efficient energy use. The author has an hindex of 11, co-authored 36 publications receiving 394 citations. Previous affiliations of Teerath Das include Chitkara University.
Papers
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Journal ArticleDOI
A Study of Today's A.I. through Chatbots and Rediscovery of Machine Intelligence
Anirudh Khanna,Bishwajeet Pandey,Kushagra Vashishta,Kartik Kalia,Bhale Pradeepkumar,Teerath Das +5 more
TL;DR: The paper shows how current approach towards A.I. is not adequate and offers a new theory that discusses machine intelligence, throwing light to the future of intelligent systems.
Journal ArticleDOI
Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA
TL;DR: This work is making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor and making this ALU portable using MOBILE DDR IO standard in place of default LVCmOS33 IO standard which the authors use in traditional ALU.
Proceedings ArticleDOI
A Quantitative and Qualitative Investigation of Performance-Related Commits in Android Apps
TL;DR: A study aimed at preliminarily investigating to what extent developers take care of performance issues in their commits, and explicitly document that found that the most predominant kinds of performance-related changes include GUI- related changes, fixing code smells, network-related code, and memory management.
Proceedings ArticleDOI
SSTL based green image ALU design on different FPGA
TL;DR: In this article, a green image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA.
Journal ArticleDOI
Thermal Mechanics Based Energy Efficient FIR Filter for Digital Signal Processing
TL;DR: Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter and there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.