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Author

Tejas Krishnamohan

Other affiliations: Intel
Bio: Tejas Krishnamohan is an academic researcher from Stanford University. The author has contributed to research in topics: MOSFET & Electron mobility. The author has an hindex of 26, co-authored 61 publications receiving 3156 citations. Previous affiliations of Tejas Krishnamohan include Intel.

Papers published on a yearly basis

Papers
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Proceedings ArticleDOI
01 Dec 2008
TL;DR: In this paper, a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS < 60 mV/dec was experimentally demonstrated.
Abstract: The main challenges for Tunnel FETs are experimentally demonstrating SS<60 mV/dec, high ON currents and solving their ambipolar behavior. We have experimentally demonstrated a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS<60 mV/dec. Due to small bandgap of s-Ge and the electrostatics of the DG structure, record high drive current of 300 uA/um (the highest ever reported experimentally for a TFET) and a subthreshold slope of ~50 mV/dec was observed. In addition, to address the ambipolar problem and examine the scalability of TFETs, we have developed a sophisticated TFET simulator that uses a Quantum transport model, Non-local BTBT, complete Bandstructure (real and complex) information, and includes all transitions (direct and phonon assisted). Using this simulator, we have studied the scalability of three asymmetric DG TFET configurations (underlapped drain, lower drain doping and lateral heterostructure) in terms of their ability to solve the ambipolar behavior and achieve high ON and low OFF currents.

515 citations

Journal ArticleDOI
TL;DR: In this article, single-crystal Ge nanowires are synthesized by a low-temperature (275°C) chemical vapor deposition (CVD) method, and Boron doped p-type GeNW field effect transistors (FETs) with back-gates and thin SiO2 (10 nm) gate insulators are constructed.
Abstract: Single-crystal Ge nanowires are synthesized by a low-temperature (275 °C) chemical vapor deposition (CVD) method. Boron doped p-type GeNW field-effect transistors (FETs) with back-gates and thin SiO2 (10 nm) gate insulators are constructed. Hole mobility higher than 600 cm2/V s is observed in these devices, suggesting high quality and excellent electrical properties of as-grown Ge wires. In addition, integration of high-κ HfO2 (12 nm) gate dielectric into nanowire FETs with top-gates is accomplished with promising device characteristics obtained. The nanowire synthesis and device fabrication steps are all performed below 400 °C, opening a possibility of building three-dimensional electronics with CVD-derived Ge nanowires.

446 citations

Journal ArticleDOI
TL;DR: In this paper, the authors show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions, and that it is possible to both under- and overestimate the interface trap density by more than an order of magnitude.
Abstract: ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

367 citations

Journal ArticleDOI
TL;DR: In this article, the authors introduced ozone oxidation to engineer Ge/insulator interface and found that the interface and Dit are strongly affected by the distribution of oxidation states and the quality of the suboxide.
Abstract: Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this letter, we introduce ozone oxidation to engineer Ge/insulator interface. Density of interface states (Dit) across the bandgap and close to the conduction band edge was extracted using conductance technique at low temperatures. Dit dependence on growth conditions was studied. Minimum Dit of 3 times 1011 cm-2V-1 was demonstrated. Physical quality of the interface was investigated through Ge 3d spectra measurements. We found that the interface and Dit are strongly affected by the distribution of oxidation states and the quality of the suboxide.

169 citations

Proceedings ArticleDOI
01 Dec 2005
TL;DR: In this article, the authors investigated the physical mechanisms of mue enhancement by uniaxial stress and quantitatively evaluated the energy surface of 2-fold valleys in Si (001) FETs.
Abstract: The physical mechanisms of mue enhancement by uniaxial stress are investigated From full band calculations, uniaxial-stress-induced split of conduction band edge, DeltaEC and effective mass change, Deltam*, are quantitatively evaluated It is experimentally and theoretically demonstrated that the energy surface of 2-fold valleys in Si (001) FETs is warped due to uniaxial lang110rang stress, resulting in lighter mT of 2-fold valleys parallel to the stress By using calculated DeltaEC and Deltam*, experimental (ie enhancement is accurately modeled for biaxial, uniaxial lang100rang, and uniaxial lang110rang stress The limits of mue enhancement and the effectiveness of uniaxial stress engineering in enhancing nFET ballistic Id,sat are also discussed

168 citations


Cited by
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Journal ArticleDOI
TL;DR: A review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches and the performance limits and advantages, when exploited for both digital and analog applications.
Abstract: The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

2,531 citations

Journal ArticleDOI
17 Nov 2011-Nature
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

2,390 citations

Journal ArticleDOI
TL;DR: It is demonstrated that through a proper understanding and design of source/drain contacts and the right choice of number of MoS(2) layers the excellent intrinsic properties of this 2-D material can be harvested.
Abstract: While there has been growing interest in two-dimensional (2-D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancy due to the lack of a complete picture of their performance potential. The focus of this article is on contacts. We demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2-D material can be harvested. Using scandium contacts on 10-nm-thick exfoliated MoS2 flakes that are covered by a 15 nm Al2O3 film, high effective mobilities of 700 cm2/(V s) are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. In fact, the apparent linear dependence of current on drain voltage had mislead researchers to believe that a truly Ohmic contact had already been achieved, a miscon...

2,185 citations

Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
Jie Xiang1, Wei Lu1, Yongjie Hu1, Yue Wu1, Hao Yan1, Charles M. Lieber1 
25 May 2006-Nature
TL;DR: Comparison of the intrinsic switching delay, τ = CV/I, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFets.
Abstract: Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

1,454 citations