T
Terence B. Hook
Researcher at IBM
Publications - 239
Citations - 4098
Terence B. Hook is an academic researcher from IBM. The author has contributed to research in topics: Transistor & Threshold voltage. The author has an hindex of 30, co-authored 239 publications receiving 3562 citations. Previous affiliations of Terence B. Hook include GlobalFoundries.
Papers
More filters
Proceedings ArticleDOI
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Nicolas Loubet,Terence B. Hook,Pietro Montanini,Chun Wing Yeung,S. Kanakasabapathy,M. Guillom,Tenko Yamashita,Jingyun Zhang,Xin Miao,Junli Wang,Albert M. Young,Robin Chao,Myounggon Kang,Zuoguang Liu,Su Chen Fan,Bassem Hamieh,Stuart A. Sieg,Yann Mignot,W. Xu,Soon-Cheon Seo,Jae-Yoon Yoo,Shogo Mochizuki,Muthumanickam Sankarapandian,Ohyun Kwon,Adra Carr,Andrew M. Greene,Young-Kwan Park,Frougier Julien,Rohit Galatage,Ruqiang Bao,Jeffrey C. Shearer,Richard A. Conti,Ho Ju Song,Deok-Hyung Lee,Dexin Kong,Y. Xu,Abraham Arceo,Zhenxing Bi,Peng Xu,Raja Muthinti,James Chingwei Li,Robert C. Wong,D. Brown,P. Oldiges,Robert R. Robison,John C. Arnold,Nelson Felix,Spyridon Skordas,John G. Gaudiello,Theodorus E. Standaert,Hemanth Jagannathan,D. Corliss,Myung-Hee Na,Andreas Knorr,T. Wu,Dinesh Gupta,S. Lian,R. Divakaruni,T. Gow,C. Labelle,Seng Luan Lee,Vamsi Paruchuri,Huiming Bu,Mukesh Khare +63 more
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Journal ArticleDOI
Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets
TL;DR: Terence Hook has been with IBM since 1980 and has worked on technology integration and device design for bipolar, BiCMOS, and CMOS technologies from 2 μm to 5 nm and beyond.
Journal ArticleDOI
Lateral ion implant straggle and mask proximity effect
Terence B. Hook,Jeffrey S. Brown,Peter E. Cottrell,Eric Adler,D. Hoyniak,J. Johnson,Randy W. Mann +6 more
TL;DR: In this article, lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices, and it is shown that threshold voltage decreases for narrow devices near the edge of the well.
Proceedings ArticleDOI
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Ruilong Xie,Pietro Montanini,Kerem Akarvardar,Neeraj Tripathi,Balasubramanian S. Pranatharthi Haran,Scott C. Johnson,Terence B. Hook,Bassem Hamieh,D. Corliss,Junli Wang,Xin Miao,John R. Sporre,Jody A. Fronheiser,Nicolas Loubet,Min Gyu Sung,Stuart A. Sieg,Shogo Mochizuki,Christopher Prindle,Soon-Cheon Seo,Andrew M. Greene,Jeffrey C. Shearer,Andre Labonte,Su Chen Fan,Lars W. Liebmann,Robin Chao,Abraham Arceo,Kisup Chung,K. Cheon,Praneet Adusumilli,H. P. Amanapu,Zhenxing Bi,Jungho Cha,H. Chen,Richard A. Conti,Rohit Galatage,Oleg Gluschenkov,Vimal Kamineni,Ki-chul Kim,Lee Choonghyun,F. Lie,Zuoguang Liu,Sanjay Mehta,Eric R. Miller,Hiroaki Niimi,Chengyu Niu,Chanro Park,D. Park,Mark Raymond,Bhagawan Sahu,Muthumanickam Sankarapandian,Shariq Siddiqui,Richard G. Southwick,Lei Sun,Charan V. V. S. Surisetty,Stan D. Tsai,S. Whang,Peng Xu,Y. Xu,C.-C. Yeh,Peter Zeitzoff,J. Zhang,James Chingwei Li,James J. Demarest,John C. Arnold,Donald F. Canaperi,Derren N. Dunn,Nelson Felix,Dinesh Gupta,Hemanth Jagannathan,S. Kanakasabapathy,Walter Kleemeier,C. Labelle,M. Mottura,P. Oldiges,Spyridon Skordas,Theodorus E. Standaert,Tenko Yamashita,Matthew E. Colburn,Myung-Hee Na,Vamsi Paruchuri,S. Lian,R. Divakaruni,T. Gow,Seng Luan Lee,Andreas Knorr,Huiming Bu,Mukesh Khare +86 more
TL;DR: In this paper, the authors present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology.
Proceedings ArticleDOI
Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
TL;DR: The comparative analysis of the intrinsic and parasitic components using the classical drift-diffusion transport and quantization models indicates that a wider and thinner stacked nanosheet-type design can address the issues associated with conventional nanowire devices while demonstrating improved performance relative to FinFET.